Verification Engineer - Semiconductor / UVM / SystemVerilog

Job Description

Verification Engineer – Semiconductor / UVM / SystemVerilog

We are recruiting Verification Engineers of all seniorities to work for a global leader in the semiconductor industry specializing in the development of cutting-edge next-CPU and GPU processors.

This is a permanent working opportunity based in Cambridge, UK.

Key responsibilities for this Verification Engineer position:

1. Actively contribute to all phases of the verification flow.
2. Take ownership in specific project areas from testbench development through to overall verification methodology.
3. Produce test plans and verification strategies.
4. Plan, track, and coordinate both individual and team tasks and ensure the quality of verification work being done.
5. Take part in verification improvement strategies across the CPU group and wider verification community.

Key Requirements:

1. A minimum of 3 years’ experience working in verification environments for complex RTL designs.
2. Knowledgeable in the use of hardware verification; eg, SystemVerilog or Specman.
3. Deep understanding of end-to-end verification processes.
4. Experience working with verification methodologies such as UVM.
5. Previous experience working on microprocessor designs.
6. Experience working with assembly, and/or C/C++.

If you are interested in this Verification Engineer position, please send a CV to .

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