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- Tasks: Develop and validate timing constraints, conduct Static Timing Analysis, and support timing closure.
- Company: Join a leading innovator in high-speed, energy-efficient chip-to-chip link solutions.
- Benefits: Enjoy hybrid remote work options and a collaborative team environment.
- Why this job: Be part of cutting-edge technology and contribute to impactful projects in the semiconductor industry.
- Qualifications: 10+ years in the semiconductor industry with strong knowledge of RTL-to-GDS flow and scripting skills.
- Other info: Excellent communication and teamwork skills are essential for success in this role.
The predicted salary is between 48000 - 72000 £ per year.
Job Description
Are you an experienced physical design engineer with a background in static timing analysis that is looking for a new role at a leading innovator in high-speed, energy-efficient chip-to-chip link solutions?
At European Tech Recruit, we are working alongside a highly innovative company, helping them to hire a senior physical design engineer in STA / timing to work on a hybrid remote basis in Northampton, UK.
Responsibilities:
- Developing and validating timing constraints, conducting sign-off Static Timing Analysis (STA), and supporting timing closure at both block and full-chip levels.
- Performing STA for both block and chip levels, working with the design team to review and define constraints, implementing SDC constraints for STA, analyzing timing violations, and resolving them with the frontend design and physical design (PD) teams.
- Contributing to the development of scripts, methodologies, and process improvements.
- Collaborating closely with the design team to meet STA requirements and implement effective solutions.
- Supporting IP and chip-level integration.
Requirements:
- Strong knowledge of RTL-to-GDS flow, including synthesis, place & route (P&R), logic equivalence checking (LEC), and STA.
- Self-driven, with a strong sense of ownership and responsibility. Excellent communication skills and a strong team player.
- Proficient in scripting (shell, TCL, Python, make) and experienced in data management (revision control systems).
- Experienced in gathering and defining SDC constraints, especially for top-level design, including DFT. Requires excellent teamwork, perseverance, attention to detail, and the ability to collaborate effectively with team members to gather information.
- Skilled in developing reusable workflows and processes across projects.
- 10+ years of experience in the semiconductor industry, with at least 5 years in a technical digital physical design role.
If interested in this role please apply here or send your email direct to .
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Physical Design Engineer - STA / Timing employer: ZipRecruiter
Contact Detail:
ZipRecruiter Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Physical Design Engineer - STA / Timing
✨Tip Number 1
Make sure to showcase your experience with static timing analysis and RTL-to-GDS flow during the interview. Be prepared to discuss specific projects where you successfully implemented SDC constraints and resolved timing violations.
✨Tip Number 2
Highlight your scripting skills, especially in shell, TCL, and Python. Consider preparing a small demo or example of a script you've developed that improved workflows or processes in your previous roles.
✨Tip Number 3
Emphasize your teamwork and communication skills. Be ready to provide examples of how you've collaborated with design teams to meet STA requirements and how you contributed to successful project outcomes.
✨Tip Number 4
Research the company’s recent projects and innovations in high-speed chip-to-chip link solutions. This knowledge will help you demonstrate your genuine interest in the role and how your background aligns with their goals.
We think you need these skills to ace Physical Design Engineer - STA / Timing
Some tips for your application 🫡
Understand the Role: Make sure you fully understand the responsibilities and requirements of the Physical Design Engineer position. Familiarize yourself with terms like Static Timing Analysis (STA), RTL-to-GDS flow, and SDC constraints to tailor your application effectively.
Highlight Relevant Experience: In your CV and cover letter, emphasize your 10+ years of experience in the semiconductor industry, particularly focusing on your 5+ years in technical digital physical design roles. Mention specific projects where you developed and validated timing constraints or performed STA.
Showcase Your Skills: Clearly outline your proficiency in scripting languages such as shell, TCL, and Python. Provide examples of how you've used these skills to improve workflows or processes in previous roles, as this aligns with the job's requirements.
Craft a Strong Cover Letter: Write a compelling cover letter that not only summarizes your qualifications but also conveys your passion for the role and the company. Discuss how your self-driven nature and teamwork skills make you a perfect fit for their innovative environment.
How to prepare for a job interview at ZipRecruiter
✨Showcase Your Technical Expertise
Be prepared to discuss your experience with RTL-to-GDS flow, including synthesis, place & route, and static timing analysis. Highlight specific projects where you successfully implemented SDC constraints and resolved timing violations.
✨Demonstrate Collaboration Skills
Since the role requires close collaboration with design teams, be ready to share examples of how you've worked effectively in a team environment. Discuss any challenges you faced and how you overcame them through teamwork.
✨Prepare for Problem-Solving Questions
Expect questions that assess your problem-solving abilities, especially related to timing closure and STA. Think of scenarios where you had to analyze timing violations and the steps you took to resolve them.
✨Highlight Your Scripting Proficiency
As scripting is a key requirement, be sure to mention your experience with shell, TCL, and Python. Prepare to discuss how you've used these skills to develop reusable workflows or improve processes in previous roles.
