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- Tasks: Develop and verify silicon in security-sensitive settings, ensuring functionality and performance.
- Company: zeroRISC is revolutionising chip security and supply chain integrity for critical sectors.
- Benefits: Join a close-knit team with opportunities for learning and career growth in a seed-stage startup.
- Why this job: Contribute to cutting-edge security solutions that protect vital systems in industrial and IoT environments.
- Qualifications: Bachelor’s degree in Electrical Engineering or Computer Science; 4 years of relevant experience required.
- Other info: Engage with the open-source silicon community and support the mission of open secure silicon.
The predicted salary is between 42000 - 63000 £ per year.
zeroRISC is redefining chip security and supply chain integrity by empowering device owners and operators in crucial sectors like silicon production, IoT, and critical infrastructure with full device ownership, control, and visibility. Led by the founders of the OpenTitan secure silicon project, zeroRISC is driving commercial adoption of high assurance software and services rooted in open silicon. Our products forge an immutable connection between hardware and software, enabling users to trust their devices no matter where they’re built or where they’re deployed.
As a zeroRISC SoC/ASIC Design Verification Engineer, you will develop, verify, and maintain silicon in security-sensitive settings, including root-of-trust technology. You will elevate and solidify zeroRISC's status as the leading provider of secure silicon IP by developing essential verification collateral. You will interact directly with zeroRISC customers to understand their requirements and deliver solutions benefitting both customer and zeroRISC alike. You will participate in the whole chip design process from architecture to tapeout and silicon validation. By engaging with the world’s premier open-source silicon community, you will support our mission of open secure silicon everywhere.
Key Responsibilities:
- Verify ASIC/SoC functionality, performance, security, and power throughout the full chip design life cycle, from test plan definition to sign-off.
- Build high quality verification environments at the chip/top and block levels following engineering best practices.
- Write thorough verification documentation including test plans.
- Diagnose, debug, and resolve regression failures and other errors.
- Achieve coverage closure.
- Ensure design functionality while upholding stringent timelines in collaboration with architecture, design, software, system, and silicon validation teams as well as engineering program managers.
What We’re Looking For:
- Bachelor’s degree in Electrical Engineering or Computer Science, or a related technical field or equivalent experience.
- 4 years of experience with simulation-based verification methodologies and languages such as UVM and SystemVerilog or formal verification-based techniques including industry standard tools.
- Experience developing and maintaining testbenches, test cases, and verification environments for simulation-based verification or formal verification environments.
Preferred Qualifications (not required):
- Master’s or PhD in Electrical Engineering or Computer Science, or a related technical field or equivalent experience.
- Knowledge of security ASICs or accelerators (e.g. cryptography accelerators or GPUs).
- Knowledge of computer architecture and memory subsystem architectures.
- Experience verifying low power designs.
- Experience with scripting languages such as Python.
Why Join Us?
- Your work will directly contribute to the development of cutting-edge security solutions, protecting critical systems in industrial and IoT environments.
- As a seed-stage startup, this role offers significant opportunities for learning and career growth.
- Join a close-knit, innovative team where you can learn, grow, and contribute to building something meaningful in the security space.
SoC/ASIC Design Verification Engineer employer: zeroRISC
Contact Detail:
zeroRISC Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land SoC/ASIC Design Verification Engineer
✨Tip Number 1
Familiarise yourself with the latest trends in ASIC and SoC design verification. Understanding current methodologies like UVM and SystemVerilog will not only boost your confidence but also show your commitment to staying updated in this fast-evolving field.
✨Tip Number 2
Engage with the open-source silicon community. Participating in forums or contributing to projects can help you build connections and demonstrate your passion for secure silicon, which is a key aspect of zeroRISC's mission.
✨Tip Number 3
Prepare to discuss your experience with security-sensitive designs during interviews. Be ready to share specific examples of how you've tackled challenges in verification processes, as this will resonate well with zeroRISC's focus on security.
✨Tip Number 4
Show enthusiasm for learning and adapting. zeroRISC values fast, flexible learners, so highlight any instances where you've quickly picked up new skills or adapted to changing project requirements in your previous roles.
We think you need these skills to ace SoC/ASIC Design Verification Engineer
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights relevant experience in ASIC/SoC design verification. Emphasise your skills with simulation-based methodologies like UVM and SystemVerilog, as well as any experience with security-sensitive projects.
Craft a Strong Cover Letter: In your cover letter, express your enthusiasm for open-source silicon and how your background aligns with zeroRISC's mission. Mention specific projects or experiences that demonstrate your ability to contribute to their goals.
Showcase Technical Skills: Include a section in your application that details your technical skills, particularly those related to verification environments, testbenches, and scripting languages like Python. This will help you stand out as a candidate.
Highlight Collaboration Experience: Since the role involves working closely with various teams, be sure to mention any past experiences where you collaborated with architecture, design, or software teams. This shows you can work effectively in a team-oriented environment.
How to prepare for a job interview at zeroRISC
✨Understand the Role
Make sure you have a solid grasp of what a SoC/ASIC Design Verification Engineer does. Familiarise yourself with key responsibilities like verifying ASIC functionality and building verification environments. This will help you answer questions confidently.
✨Showcase Your Technical Skills
Be prepared to discuss your experience with simulation-based verification methodologies, particularly UVM and SystemVerilog. Bring examples of past projects where you've developed testbenches or resolved regression failures to demonstrate your expertise.
✨Engage with the Open Source Community
Since zeroRISC values open-source contributions, mention any involvement you have in the open-source silicon community. Discussing relevant projects or collaborations can show your commitment to the mission of open secure silicon.
✨Prepare Questions for Them
Interviews are a two-way street. Prepare insightful questions about their current projects, team dynamics, or future goals. This not only shows your interest but also helps you assess if the company aligns with your career aspirations.