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- Tasks: Lead the design of cutting-edge RTL for satellite communications and mentor junior engineers.
- Company: Fast-growing deep-tech company at the forefront of satellite technology.
- Benefits: Competitive salary, equity, pension, private medical, and hybrid work options.
- Why this job: Join a high-calibre team and shape the future of 5G communications in space.
- Qualifications: Extensive experience in Verilog/SystemVerilog and delivering high-throughput FPGA/ASIC IP.
- Other info: Opportunity to influence product direction and engineering methodology.
The predicted salary is between 72000 - 108000 £ per year.
Location: Southampton, UK (Hybrid)
Package: Competitive base salary + equity + pension + private medical
A well-funded, fast-growing deep-tech company is developing high-performance signal processing technology for deployment onboard satellites. They are looking to appoint a Lead FPGA Design Engineer to take a central role in shaping and delivering complex RTL designs for FPGA (and ASIC) targets. This is a senior, hands-on role where technical excellence and delivery ownership go hand in hand. The successful candidate will lead key projects, mentor junior engineers, and drive the development of optimised, production-ready IP for advanced Layer 1 systems. This is a rare opportunity to join a high-calibre team working at the forefront of next-generation satellite communications, with significant scope to influence both product direction and engineering methodology.
What they’re looking for:
- Extensive experience developing complex digital designs in Verilog or SystemVerilog
- Strong track record delivering high-throughput FPGA or ASIC IP, ideally in signal processing or comms applications
- Expertise in simulation, synthesis, timing optimisation, and lab-based validation
Principal IC Design Engineer employer: Yoh Solutions
Contact Detail:
Yoh Solutions Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Principal IC Design Engineer
✨Tip Number 1
Network like a pro! Reach out to your connections in the industry, especially those who work in satellite communications or FPGA design. A friendly chat can lead to insider info about job openings that aren't even advertised yet.
✨Tip Number 2
Show off your skills! Prepare a portfolio showcasing your best RTL designs and projects. When you get the chance to chat with potential employers, having tangible examples of your work can really set you apart from the crowd.
✨Tip Number 3
Practice makes perfect! Get ready for technical interviews by brushing up on your Verilog and SystemVerilog knowledge. Consider mock interviews with friends or colleagues to build confidence and refine your answers.
✨Tip Number 4
Apply through our website! We’ve got a streamlined application process that makes it easy for you to showcase your talents. Plus, it shows you're genuinely interested in joining our team at the forefront of next-gen satellite communications.
We think you need these skills to ace Principal IC Design Engineer
Some tips for your application 🫡
Tailor Your CV: Make sure your CV is tailored to the role of Principal IC Design Engineer. Highlight your experience with Verilog or SystemVerilog and any relevant projects you've worked on in signal processing or communications. We want to see how your skills match what we're looking for!
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you're passionate about satellite communications and how your background makes you a perfect fit for our team. Don’t forget to mention any leadership experience, as mentoring junior engineers is key in this role.
Showcase Your Projects: If you've worked on any complex RTL designs or FPGA/ASIC projects, make sure to showcase them in your application. We love seeing real examples of your work, so include details about your contributions and the impact they had on the project.
Apply Through Our Website: We encourage you to apply through our website for a smoother process. It helps us keep track of applications and ensures you get all the updates directly from us. Plus, it shows you're keen on joining our team at StudySmarter!
How to prepare for a job interview at Yoh Solutions
✨Know Your RTL Inside Out
Make sure you brush up on your RTL design skills, especially in Verilog or SystemVerilog. Be prepared to discuss your past projects in detail, focusing on the challenges you faced and how you overcame them. This will show your technical depth and problem-solving abilities.
✨Showcase Your Leadership Skills
Since this role involves mentoring junior engineers, be ready to share examples of how you've led teams or projects in the past. Highlight any experiences where you guided others through complex designs or helped improve processes. This will demonstrate your capability to take ownership and lead effectively.
✨Understand the Company’s Vision
Research the company’s focus on satellite communications and their specific technologies. Being able to articulate how your skills align with their goals will set you apart. Show enthusiasm for their mission and how you can contribute to their innovative projects.
✨Prepare for Technical Questions
Expect in-depth technical questions related to FPGA and ASIC design, simulation, and timing optimisation. Practise explaining your thought process clearly and concisely. Consider doing mock interviews with peers to refine your responses and boost your confidence.