Design Verification Engineer in Southampton

A communications technology company is preparing to take proven Layer 1 IP from FPGA into ASIC.

Recent commercial success within the satellite communications market has created the need to scale engineering capability as products move towards high-volume deployment.

As part of that growth, they're looking for a Senior Verification Engineer to take ownership of UVM-based verification across complex communications IP.

Working closely with architects, RTL designers and systems engineers, you'll be involved from specification through to sign-off, developing verification plans, building SystemVerilog/UVM environments, creating coverage models and debugging issues across both RTL and verification environments.

You'll likely bring

• SystemVerilog and UVM experience
• ASIC and/or FPGA verification experience
• Coverage-driven and assertion-based verification
• Linux and scripting skills (Python, Tcl or Bash)
• Strong debugging and problem-solving skills

Experience within wireless communications, DSP, modem development, Layer 1 processing or satellite communications would be beneficial, but is not essential.

Why this opportunity is different

The technology already works.

The challenge now is scaling it.

You'll join at a point where verification is becoming increasingly important as communications IP moves from FPGA-based implementations towards ASIC deployment, working within a team where verification engineers have visibility, influence and direct access to the architects and designers developing the technology.