TRIA seeks a Senior RTL Design Engineer to lead RTL architecture and digital top-level integration for its photonic compute path. You will define the digital architecture, clock/reset strategy and interfaces, and write synthesizable RTL for control state machines and data paths.
Collaborate across photonics, analog, verification and layout teams through tapeout and first-silicon bring-up. 8+ years in ASIC RTL design with SystemVerilog, timing constraints and high-speed interfaces is required.
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Lead RTL Design Engineer for Photonic Compute Path in Leeds employer: TRIA
Tria is an exceptional employer that fosters a dynamic work culture, offering hybrid working arrangements that promote work-life balance. With a strong focus on employee growth and development, Tria provides opportunities for professional advancement while leading transformative projects in the North West. Join a team that values innovation and collaboration, ensuring you play a pivotal role in shaping the future of enterprise infrastructure.
