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- Tasks: Develop testbenches and ensure verification coverage for non-volatile memory IP.
- Company: Tessolve Semiconductors provides end-to-end design and test engineering solutions globally.
- Benefits: Enjoy competitive compensation, skill development opportunities, and a vibrant work environment.
- Why this job: Join a dynamic team and contribute to innovative technology in a global company.
- Qualifications: 5+ years of experience in Digital IP verification using SystemVerilog/UVM required.
- Other info: Remote work options available with occasional visits to Bristol or Munich.
The predicted salary is between 36000 - 60000 £ per year.
JOB DESCRIPTION
Title/Position: Verification SV/UVM for TC48x NVM
Location: EU/UK – The candidate is ideally based in Bristol, UK or Munich, Germany
If this is not possible then the candidate should be prepared for occasional on-site visits to
Bristol or Munich.
SL.NO: I2
Key Responsibilities:
1) Develop testbenches for a non-volatile memory IP
2) Creation of agents
3) Make adaptations to existing and create new tests for new features of the NVM IP
4) Show that the relevant tests are passing
5) Define verification coverage
6) Testbench Qualification using Certitude
7) Documentation of verification results
8) Proof that relevant tests are passing
9) Proof that verification coverage (structural and functional) is reached
10) Proof that the testbenches have the required quality
TSMC relevant-yes
Proven experience (>5 years) in Digital IP verification using System Verilog / UVM
About us:
Tessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service
Company providing End to End Solutions from Product Engineering, Software, Hardware,
Wireless, Automotive and Embedded Solutions.
Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an
efficient turnkey solution for silicon bring-up, spec to the product. With 2500+ employees
worldwide,
Tessolve provides a one-stop-shop solution with full-fledged hardware and software
capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey
ASIC Solution, from design to packaged parts. We have a global presence with office locations in
the United States, India, Singapore, Malaysia, Germany, United Kingdom, China, UK, Japan,
Thailand, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose.
Tessolve offers a highly competitive compensation and benefits along with an electric work
environment to scale one’s intellect, skills and growth
Design Verification Engineer employer: Tessolve
Contact Detail:
Tessolve Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Design Verification Engineer
✨Tip Number 1
Familiarise yourself with SystemVerilog and UVM if you haven't already. Brush up on your knowledge of testbench development and verification methodologies, as these are crucial for the role.
✨Tip Number 2
Network with professionals in the semiconductor industry, especially those who work in verification roles. Attend relevant meetups or online forums to gain insights and potentially get referrals.
✨Tip Number 3
Prepare to discuss specific projects where you've developed testbenches or worked with non-volatile memory IP. Be ready to explain your approach and the outcomes of your work.
✨Tip Number 4
Research Tessolve Semiconductors and their projects. Understanding their work culture and recent developments can help you tailor your conversation during interviews and show your genuine interest.
We think you need these skills to ace Design Verification Engineer
Some tips for your application 🫡
Understand the Role: Before applying, make sure you fully understand the responsibilities of a Design Verification Engineer. Familiarise yourself with terms like SystemVerilog and UVM, as well as the specific requirements mentioned in the job description.
Tailor Your CV: Highlight your relevant experience in digital IP verification, especially any work you've done with SystemVerilog and UVM. Make sure to include specific projects or achievements that demonstrate your skills in developing testbenches and ensuring verification coverage.
Craft a Compelling Cover Letter: Write a cover letter that not only outlines your qualifications but also expresses your enthusiasm for the role at Tessolve Semiconductors. Mention why you're interested in their work and how your background aligns with their needs.
Proofread Your Application: Before submitting, carefully proofread your CV and cover letter for any errors or typos. A polished application reflects your attention to detail, which is crucial for a role in verification engineering.
How to prepare for a job interview at Tessolve
✨Showcase Your Technical Skills
As a Design Verification Engineer, it's crucial to demonstrate your expertise in SystemVerilog and UVM. Be prepared to discuss specific projects where you've developed testbenches or created agents, and highlight any challenges you overcame during the verification process.
✨Understand the Company’s Products
Familiarise yourself with Tessolve Semiconductors' offerings, especially their non-volatile memory IP. Understanding their products will allow you to tailor your responses and show genuine interest in how your skills can contribute to their success.
✨Prepare for Scenario-Based Questions
Expect questions that assess your problem-solving abilities in real-world scenarios. Prepare examples from your past experience where you ensured verification coverage or documented results effectively, as this will showcase your practical knowledge.
✨Ask Insightful Questions
At the end of the interview, ask questions that reflect your interest in the role and the company. Inquire about the team dynamics, ongoing projects, or future technologies they are exploring. This shows that you are not only interested in the position but also in contributing to the company's growth.
