IC Package Designer / Developer in Cambridge

Location: Cambridge, United Kingdom

About Tessolve Semiconductors

Tessolve Semiconductors, a venture of Hero Electronix, is a design and test engineering service company providing end‑to‑end solutions from product engineering, software, hardware, wireless, automotive and embedded solutions. Tessolve offers a unique combination of pre‑silicon and post‑silicon expertise to provide an efficient turnkey solution for silicon bring‑up, spec to product. With 2,500+ employees worldwide, Tessolve provides a one‑stop‑shop solution with full‑fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a turnkey ASIC solution, from design to packaged parts. We have a global presence with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, China, Japan, Thailand, Philippines and test labs in India, Singapore, Malaysia, Austin, San Jose.

IC Package Designer / Developer

We are looking for an experienced packaging designer to develop creative and cost‑effective packaging designs.

Responsibilities

• Netlist creation, BGA creation as per the inputs
• Conduct feasibility studies to advise optimum pad layout, interconnect types and substrate parameters for a specific IC device or application
• Define substrate stack‑ups, routing strategies and via structures
• Substrate design experience for RF, digital, high‑speed and mixed signal die
• Excellent understanding of SI/PI requirements for routing HSIO (DDR, SERDES, etc.)
• Good experience in UCIE‑Advanced and Standard technology, HBM technology
• Experience in setting design rule checks (DRC) to ensure layouts meet specific manufacturing, assembly and design guidelines
• Experience of optimising the die breakout for signals and creating patterns for high power
• Strong understanding of HDI substrate technologies, layout design rules, and materials for optimal performance. Verify designs against electrical, thermal, mechanical, and manufacturability requirements
• Hands‑on experience with Wire bond, Flip chip & advanced packaging technologies (2.5D, 3D, RDL, embedded passives, etc.)
• Strong experience with CoWoS (Chip‑on‑Wafer‑on‑Substrate) interposer design and the impact of the substrate design to support CoWoS
• Knowledge of different OSAT design rules

Qualifications

• Bachelor’s degree in Electronics / Electrical Engineering
• 3 to 8+ years in IC package design and development
• Proficiency with Cadence Allegro Package Designer

Share resume: amritanshuman.swain@tessolve.com

Details

• Seniority level: Mid‑Senior level
• Employment type: Full‑time
• Job function: Engineering and Information Technology
• Industries: Semiconductor Manufacturing