Senior Verification Engineer in Reading

A Senior Mixed Signal Verification Engineer will join an exciting Semiconductor Scale-up to undertake digital, mixed signal and analog verification related to high speed Serdes designs. Youll bring 10 years Verification experience, strong Scripting skills and extensive experience with Cadence tools. This exciting High-Tech Company is leading the development of high-speed and energy efficient chip-chip link solutions revolutionizing wired connectivity around the World. The talented team seeks a Degree qualified Senior level Mixed Signal Verification Engineer to join them in this growth. Skills and Experience should include: Extensive experience of digital/mixed signal analog Verification with test bench design, connect modules, electrical/discrete partitioning. Good Scripting skills. Cadence APS, SpectreX / digital solver. System Verilog Assertions. Cadence Virtuoso Framework: Schematic editor, Assembler, AMS. High-speed communication systems such as SerDes. Good digital verification background with some Specman/SV UVM exposure and/or analog verification background. A competitive salary will be offered with Hybrid working, Shares and numerous benefits.