Hybrid Digital Design Engineer RTL & SoC Architect

Hybrid Digital Design Engineer RTL & SoC Architect

Full-Time 55000 - 70000 Β£ / year (est.) No working from home possible
Talanto

At a Glance

  • Tasks: Design cutting-edge digital circuits for SoCs and collaborate on innovative mixed-signal products.
  • Company: Join Cirrus Logic, a leader in advanced technology and innovation.
  • Benefits: Competitive salary, relocation support, and opportunities for mentorship and growth.
  • Other info: Dynamic team environment with a focus on quality and innovation.
  • Why this job: Be at the forefront of technology, shaping the future of digital design.
  • Qualifications: Experience in digital design and a passion for mentoring others.

The predicted salary is between 55000 - 70000 Β£ per year.

Cirrus Logic is seeking a Digital Design Engineer (Hardware) to develop digital circuit architectures for So Cs on advanced process nodes, from concept to production.

You will collaborate with a team on complex mixed-signal products and IPs, focusing on digital system-level design and clock/reset architectures.

Based in Newbury, England, or willing to relocate within a commutable distance, with an emphasis on IP quality, design reviews, and mentoring junior engineers.

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Hybrid Digital Design Engineer RTL & SoC Architect employer: Talanto

Almedia is an exceptional employer that fosters a dynamic and innovative work culture, perfect for those passionate about machine learning and real-time personalization. With a strong emphasis on employee growth, you will have the opportunity to mentor fellow engineers while collaborating with cross-functional teams in the vibrant city of London. The hybrid working arrangements and commitment to impactful projects make Almedia a rewarding place to advance your career in AdTech.

Talanto

Contact Details:

Talanto Recruitment Team

We think you need these skills to ace Hybrid Digital Design Engineer RTL & SoC Architect

Digital Circuit Design
SoC Architecture
Mixed-Signal Products
IP Development
System-Level Design
Clock/Reset Architectures
Design Reviews