At a Glance
- Tasks: Transform netlists into GDSII designs and optimise high-performance cores.
- Company: Leading semiconductor company focused on innovation and technology.
- Benefits: Attractive salary, flexible working options, and opportunities for skill development.
- Other info: Fast-paced environment with significant potential for career advancement.
- Why this job: Join a team shaping the future of chip design with cutting-edge technology.
- Qualifications: Experience in physical design and proficiency with EDA tools like Synopsys ICC.
The predicted salary is between 50000 - 65000 £ per year.
Job Description & Requirements
- Netlist to GDSII at block level, Subsystem Level and at Full chip.
- Worked on multiple tapeouts on Netlist to GDSII
- Hierarchical partitioning and budgeting of block-level subsystems.
- Implementation of high performance (HP) cores, low power designs
- Node experience upto 7nm, 10nm, 14nm, 28nm.
- Timing Signoff in loop through STA and ECO cycle at block and at interface.
- Block level floor planning, power planning and IR drop analysis.
- Scan chain reordering / Scan Chain repartitioning
- CTS expertise and clock tree constraints creation for meeting specifications
- MMMC optimization at Block and Sub-System Level
- Timing closure with Crosstalk and AOCV / POCV
- TCL scripting to fundamentally understand tool usage.
- MANDATORY EDA SKILLS
- Pn R tools such as Synopsys ICC/ICC2 and/or Cadence Innovus
- #J-18808-Ljbffr
Physical Design Engineer II in Penarth employer: SVENTL ASIA PACIFIC PTE. LTD.
As a Physical Design Engineer II at our company, you will thrive in a dynamic and innovative environment that prioritises employee growth and collaboration. We offer competitive benefits, a supportive work culture, and opportunities to work on cutting-edge technology in a location known for its vibrant tech community, ensuring your contributions are both meaningful and rewarding.
Contact Details:
SVENTL ASIA PACIFIC PTE. LTD. Recruitment Team
We think you need these skills to ace Physical Design Engineer II in Penarth
Netlist to GDSII
Hierarchical Partitioning
Budgeting of Block-Level Subsystems
High Performance Cores Implementation
Low Power Designs
Node Experience (7nm, 10nm, 14nm, 28nm)
Timing Signoff
