FPGA Design Engineer

Our client is a technology-oriented company developing advanced quantum networking hardware and photonic technologies for next-generation quantum computing systems.

The organization develops highly integrated engineering solutions designed to improve the scalability, performance, and practical deployment of quantum information systems.

Its activities combine electronics, photonics, physics, nanofabrication, mechanical engineering, software, and FPGA development within a highly multidisciplinary environment.

The company operates from early-stage concepts and circuit development through laboratory testing, system integration, and prototype deployment, offering engineers the opportunity to work on technically demanding hardware at the forefront of quantum technology.

Mission

The FPGA Design Engineer will be responsible for developing, verifying, and supporting FPGA-based real-time control systems for quantum networking applications.

The role will contribute to existing hardware platforms based on ARTIQ and the Sinara hardware ecosystem while supporting the development of next-generation control infrastructure incorporating White Rabbit technology, working closely with senior engineers and multidisciplinary technical teams.

Responsibilities

• FPGA and Embedded Development
• Design, develop, and verify RTL code using System Verilog, Verilog, VHDL and/or Migen for Xilinx Zynq and Ultra Scale devices.
• Design, develop, and verify embedded software in C and/or Rust.
• Support the development and verification of FPGA and embedded hardware subsystems in collaboration with senior engineers.
• Real-Time Control and Hardware Integration
• Develop, debug, and verify real-time control systems using ARTIQ and Sinara hardware.
• Support hardware bring-up and deployment of control systems within multi-node quantum networking platforms.
• Contribute to debugging tools that provide in-system visibility into real-time system behaviour.
• Verification and Development Infrastructure
• Develop and execute verification activities, testbenches, and test plans for FPGA-based systems.
• Contribute to automation of engineering tool flows, CI/CD pipelines, and automated release processes.
• Support debugging, synthesis, timing closure, and verification activities throughout the FPGA development lifecycle.
• Multidisciplinary Engineering and Documentation
• Collaborate with physicists, optical engineers, electronics engineers, and software engineers to define requirements, capture specifications, and develop appropriate technical solutions.
• Contribute to design documentation, test plans, and technical reports.
• Support technical investigation and problem solving across FPGA, embedded, and wider control-system interfaces.
• Required Qualifications
• Proficiency in System Verilog, Verilog and/or VHDL, with a solid understanding of RTL design principles.
• Hands-on experience with Xilinx or Altera FPGA device families.
• Familiarity with communication protocols and hardware interfaces including SPI, I2C, and Ethernet.
• Experience using testbenches for verification and exposure to constrained-random verification.
• Knowledge of clock-domain crossing checks, synthesis, and timing closure.
• Experience with scripting languages, preferably Python.
• Strong written and verbal communication skills for technical documentation and reporting.
• Curiosity and a proactive approach to learning new concepts, technologies, tools, and engineering practices.
• Preferred Experience
• Experience developing low-latency and/or real-time systems.
• Experience debugging Arm or RISC-V CPU subsystems using GDB, debuggers, and trace tools.
• Experience developing embedded software in C or Rust.
• Experience with Cocotb and/or System Verilog verification, System Verilog Assertions, and formal verification workflows.
• Experience with RF signal generation and processing, including Direct Digital Synthesis, RF communication protocols, and modulation techniques.
• Experience working with high-speed DACs and ADCs for RF and mixed-signal applications.
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