FPGA Engineer Intern β€” Verilog, Python, Vivado

FPGA Engineer Intern β€” Verilog, Python, Vivado

Full-Time 120000 - 120000 Β£ / year (est.) No working from home possible
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At a Glance

  • Tasks: Design and develop FPGA/SoC solutions using Verilog and Python.
  • Company: Join Stars Arena, a cutting-edge tech company in Cambridge.
  • Benefits: Earn up to Β£600 per day as an intern.
  • Other info: Exciting opportunity to work in a dynamic tech environment.
  • Why this job: Gain hands-on experience with advanced AMD Xilinx UltraScale devices.
  • Qualifications: Proficiency in System Verilog and RTL design required.

The predicted salary is between 120000 - 120000 Β£ per year.

Stars Arena is looking for an FPGA Engineer to join their team in Cambridge, United Kingdom. The role requires expertise in FPGA/SoC design and RTL skills particularly in System Verilog. Candidates should have hands-on experience with AMD Xilinx UltraScale devices using the Vivado tool suite. The position is an intern role with compensation of up to Β£600 per day. Unfortunately, visa sponsorship is not provided and no additional benefits are listed.

FPGA Engineer Intern β€” Verilog, Python, Vivado employer: Stars Arena

Stars Arena offers an exceptional opportunity for aspiring FPGA Engineers to gain hands-on experience in a dynamic and innovative environment in Cambridge. With a focus on cutting-edge technology and a collaborative work culture, interns can expect to develop their skills while contributing to exciting projects. The competitive compensation reflects the company's commitment to attracting top talent, making it an ideal place for those seeking meaningful and rewarding employment.

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Contact Details:

Stars Arena Recruitment Team

We think you need these skills to ace FPGA Engineer Intern β€” Verilog, Python, Vivado

FPGA Design
SoC Design
RTL Skills
System Verilog
AMD Xilinx UltraScale
Vivado Tool Suite
Python