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- Tasks: Design high-performance IP for next-gen FPGA/Adaptive SoC technologies and collaborate with top engineering teams.
- Company: Join Tata Consultancy Services, a leading transformation company with innovative projects.
- Benefits: Remote work, diverse environment, and opportunities for professional growth.
- Why this job: Shape the future of technology while expanding your technical skills in a dynamic role.
- Qualifications: Expertise in System Verilog RTL and experience with FPGA/Adaptive SoC design.
- Other info: Contract role with potential for extension based on performance.
The predicted salary is between 36000 - 60000 £ per year.
Location: Belfast, UK (Remote)
Job Type: Contract (Inside IR35)
Duration: 6 months, with the potential for extension based on project needs and performance
Job Summary: Join Tata Consultancy Services (TCS) as a Senior IP Design Engineer and play a key role in designing high-performance IP for next-generation FPGA/Adaptive SoC technologies. Work remotely on impactful projects that help shape the future of FPGA and SoC design, collaborating with top-tier engineering teams and expanding your technical horizons.
About the Company: TCS is a leading transformation company partnering with some of the world's biggest brands. At TCS, you'll be part of innovative, challenging projects that drive real impact and support your professional growth in a diverse, inclusive environment.
Key Responsibilities:
- Design high-performance IP targeting FPGA/Adaptive SoC technology using System Verilog RTL.
- Deliver synthesis-ready designs that meet timing and integration requirements.
- Collaborate with engineering teams to ensure quality and performance targets are met.
Skills, Experience, and Abilities Required:
- Expertise in System Verilog RTL design
- Hands-on experience with 100Gb Ethernet, PCIe Gen5, AMBA/AXI
- In-depth knowledge of FPGA/Adaptive SoC design flow, including place & route (P&R) and timing closure
- Proficiency in Vivado/Vitis
- Strong scripting skills in Python and Tcl
- Experience with Git and CI/CD
Additional Information:
Remote role: No regular office attendance required.
Senior IP Design Engineer in Peterborough employer: Stackstudio Digital Ltd.
Contact Detail:
Stackstudio Digital Ltd. Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Senior IP Design Engineer in Peterborough
✨Tip Number 1
Network like a pro! Reach out to your connections in the industry, especially those who work at TCS or similar companies. A friendly chat can open doors and give you insider info on the role.
✨Tip Number 2
Show off your skills! Prepare a portfolio or a project showcase that highlights your expertise in System Verilog RTL and FPGA design. This will help you stand out during interviews and discussions.
✨Tip Number 3
Practice makes perfect! Brush up on common interview questions related to IP design and FPGA technologies. Mock interviews with friends or mentors can help you feel more confident.
✨Tip Number 4
Apply through our website! We make it easy for you to submit your application directly, ensuring it gets the attention it deserves. Plus, you’ll be one step closer to landing that dream job!
We think you need these skills to ace Senior IP Design Engineer in Peterborough
Some tips for your application 🫡
Tailor Your CV: Make sure your CV is tailored to the Senior IP Design Engineer role. Highlight your expertise in System Verilog RTL and any hands-on experience with 100Gb Ethernet or PCIe Gen5. We want to see how your skills align with what we're looking for!
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you're passionate about FPGA/Adaptive SoC design and how your previous projects have prepared you for this role. Let us know what excites you about working with TCS.
Showcase Your Projects: If you've worked on relevant projects, don't hold back! Include links or descriptions of your work that demonstrate your proficiency in Vivado/Vitis and scripting skills in Python and Tcl. We love seeing real examples of your capabilities.
Apply Through Our Website: We encourage you to apply through our website for a smoother application process. It helps us keep track of your application and ensures you don’t miss out on any important updates. Plus, it’s super easy!
How to prepare for a job interview at Stackstudio Digital Ltd.
✨Know Your Stuff
Make sure you brush up on your System Verilog RTL design skills and be ready to discuss your hands-on experience with 100Gb Ethernet, PCIe Gen5, and AMBA/AXI. The interviewers will likely want to dive deep into your technical expertise, so having specific examples from your past projects can really set you apart.
✨Showcase Your Collaboration Skills
Since the role involves working closely with engineering teams, be prepared to talk about how you've successfully collaborated in the past. Share examples of how you ensured quality and performance targets were met, and highlight any tools or processes you used to facilitate teamwork.
✨Demonstrate Your Problem-Solving Abilities
Be ready to tackle some technical challenges during the interview. Practise explaining your thought process when faced with design issues, especially around timing closure and integration requirements. This will show that you can think critically and adapt to complex situations.
✨Familiarise Yourself with Tools
Since proficiency in Vivado/Vitis and scripting in Python and Tcl is essential, make sure you're comfortable discussing these tools. If you have experience with Git and CI/CD, mention how you've used them in your previous roles to streamline your workflow and improve project outcomes.
