Find a job 
Featured Companies 
Featured Universities 
For Companies At a Glance
- Tasks: Design and optimise IP for high-performance Adaptive SoCs using cutting-edge technologies.
- Company: Join a leading tech firm in Cambridge, London, or Milton Keynes with a hybrid work model.
- Benefits: Enjoy competitive pay, flexible working, and opportunities for professional growth.
- Why this job: Make a real impact in the tech world while collaborating with talented teams.
- Qualifications: Experience in SystemVerilog, high-speed protocols, and FPGA/Adaptive SoC development required.
- Other info: Dynamic role with excellent career advancement opportunities in a collaborative environment.
The predicted salary is between 54000 - 84000 £ per year.
Location: Cambridge OR London OR Milton Keynes (Hybrid- 1-2 Days)
Duration: Fixed term contract
Job Overview:
Scope of Work
The selected engineer will work closely with internal architecture, RTL, verification, and integration teams to design, implement, and optimize IP targeting AMD Adaptive SoCs.
Responsibilities include:
- Developing RTL in SystemVerilog for high-performance FPGA / Adaptive SoC designs
- Implementing and optimizing high-speed connectivity protocols
- Collaborating with cross-functional teams on integration, timing closure, and validation
- Driving improvements across synthesis, place and route, and timing flows
- Supporting CI/CD development workflows using Git and scripting automation
Required Skills & Experience
The proposed candidate must meet the following qualifications:
- RTL Design & Coding - Deep hands-on experience with SystemVerilog HDL for RTL design. Proven ability to develop IP targeting FPGA / Adaptive SoC platforms.
- High-Speed Protocols - Strong experience with: 100Gb Ethernet, PCIe Gen5, AMBA / AXI interface protocols.
- Adaptive SoC / FPGA Expertise - In-depth understanding of FPGA / Adaptive SoC development flows, including: Synthesis, Place and route, Timing analysis and closure.
- AMD Toolchain Experience - Hands-on experience with AMD Vivado / Vitis tools and associated flows.
- Scripting & Automation - Proficiency in scripting: Python, Tcl. Able to automate design, build, and verification workflows. Comfortable with Git for CI/CD integration.
Deliverables:
- RTL IP blocks developed in SystemVerilog according to project specification
- Timing-closed design implementations for target Adaptive SoCs
- Documentation for IP integration and usage
- Scripts and automation to support CI/CD workflows
- Weekly status updates and participation in technical reviews
Senior IP Design Engineer in Leicester employer: Stackstudio Digital Ltd.
Contact Detail:
Stackstudio Digital Ltd. Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Senior IP Design Engineer in Leicester
✨Tip Number 1
Network like a pro! Reach out to your connections in the industry, especially those who work with Adaptive SoCs or FPGA designs. A friendly chat can lead to insider info about job openings that aren't even advertised yet.
✨Tip Number 2
Show off your skills! Create a portfolio showcasing your best RTL designs and projects. This is your chance to demonstrate your expertise in SystemVerilog and high-speed protocols like PCIe Gen5. Make it easy for potential employers to see what you can do!
✨Tip Number 3
Prepare for interviews by brushing up on your knowledge of AMD tools like Vivado and Vitis. Be ready to discuss your experience with timing analysis and closure, as well as how you've tackled challenges in previous projects. Confidence is key!
✨Tip Number 4
Don't forget to apply through our website! We love seeing candidates who are proactive. Plus, it gives you a better chance to stand out in the application process. Let's get you that Senior IP Design Engineer role!
We think you need these skills to ace Senior IP Design Engineer in Leicester
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your experience with SystemVerilog and any relevant high-speed protocols. We want to see how your skills align with the role, so don’t be shy about showcasing your expertise in FPGA and Adaptive SoC development.
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re passionate about IP design and how your background makes you a perfect fit for our team. We love seeing enthusiasm and a bit of personality!
Showcase Your Projects: If you've worked on any projects involving AMD tools or scripting automation, make sure to mention them. We appreciate candidates who can demonstrate their hands-on experience and problem-solving skills through real-world examples.
Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you don’t miss out on any important updates. Plus, we love seeing applications come in through our own channels!
How to prepare for a job interview at Stackstudio Digital Ltd.
✨Know Your RTL Inside Out
Make sure you brush up on your SystemVerilog skills. Be ready to discuss your hands-on experience with RTL design and how you've tackled challenges in previous projects. Prepare to share specific examples of IP targeting FPGA or Adaptive SoC platforms you've worked on.
✨Familiarise Yourself with High-Speed Protocols
Since the role requires strong experience with protocols like 100Gb Ethernet and PCIe Gen5, it’s crucial to understand these inside and out. Be prepared to explain how you've implemented and optimised these protocols in past projects, and think about any challenges you faced and how you overcame them.
✨Show Off Your Collaboration Skills
This position involves working closely with cross-functional teams, so be ready to discuss your experience collaborating with architecture, verification, and integration teams. Share examples of how you’ve contributed to successful project outcomes through teamwork and communication.
✨Demonstrate Your Scripting Savvy
Proficiency in scripting is key for this role. Brush up on your Python and Tcl skills, and be prepared to talk about how you've used automation to streamline design, build, and verification workflows. Highlight any experience you have with Git for CI/CD integration as well.
