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For Companies At a Glance
- Tasks: Design and optimise IP for high-performance Adaptive SoCs using cutting-edge technologies.
- Company: Join a leading tech firm in Cambridge, London, or Milton Keynes with a hybrid work model.
- Benefits: Enjoy competitive pay, flexible working, and opportunities for professional growth.
- Why this job: Make a real impact in the tech world while collaborating with talented teams.
- Qualifications: Experience in SystemVerilog, high-speed protocols, and FPGA/Adaptive SoC development required.
- Other info: Dynamic role with excellent career advancement opportunities in a collaborative environment.
The predicted salary is between 54000 - 84000 £ per year.
Location: Cambridge OR London OR Milton Keynes (Hybrid- 1-2 Days)
Duration: Fixed term contract
Job Overview:
Scope of Work
The selected engineer will work closely with internal architecture, RTL, verification, and integration teams to design, implement, and optimize IP targeting AMD Adaptive SoCs.
Responsibilities include:
- Developing RTL in SystemVerilog for high-performance FPGA / Adaptive SoC designs
- Implementing and optimizing high-speed connectivity protocols
- Collaborating with cross-functional teams on integration, timing closure, and validation
- Driving improvements across synthesis, place and route, and timing flows
- Supporting CI/CD development workflows using Git and scripting automation
Required Skills & Experience
The proposed candidate must meet the following qualifications:
- RTL Design & Coding - Deep hands-on experience with SystemVerilog HDL for RTL design. Proven ability to develop IP targeting FPGA / Adaptive SoC platforms.
- High-Speed Protocols - Strong experience with: 100Gb Ethernet, PCIe Gen5, AMBA / AXI interface protocols.
- Adaptive SoC / FPGA Expertise - In-depth understanding of FPGA / Adaptive SoC development flows, including: Synthesis, Place and route, Timing analysis and closure.
- AMD Toolchain Experience - Hands-on experience with AMD Vivado / Vitis tools and associated flows.
- Scripting & Automation - Proficiency in scripting: Python, Tcl. Able to automate design, build, and verification workflows. Comfortable with Git for CI/CD integration.
Deliverables
- RTL IP blocks developed in SystemVerilog according to project specification
- Timing-closed design implementations for target Adaptive SoCs
- Documentation for IP integration and usage
- Scripts and automation to support CI/CD workflows
- Weekly status updates and participation in technical reviews
Senior IP Design Engineer in Ipswich employer: Stackstudio Digital Ltd.
Contact Detail:
Stackstudio Digital Ltd. Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Senior IP Design Engineer in Ipswich
✨Tip Number 1
Network like a pro! Reach out to folks in the industry, especially those working with Adaptive SoCs or FPGA designs. Attend meetups or webinars, and don’t be shy about asking for informational interviews – you never know who might have a lead on your dream job!
✨Tip Number 2
Show off your skills! Create a portfolio showcasing your RTL designs and any projects you've worked on with high-speed protocols. This can really set you apart from other candidates and give potential employers a taste of what you can bring to the table.
✨Tip Number 3
Prepare for technical interviews by brushing up on SystemVerilog and the AMD toolchain. Practice coding challenges and be ready to discuss your past projects in detail. We want to see how you think and solve problems, so be ready to showcase your expertise!
✨Tip Number 4
Don’t forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, we love seeing candidates who are proactive and engaged with our company. Let’s get you that Senior IP Design Engineer role!
We think you need these skills to ace Senior IP Design Engineer in Ipswich
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your experience with SystemVerilog and any relevant projects you've worked on. We want to see how your skills align with the role, so don’t be shy about showcasing your expertise in high-speed protocols and Adaptive SoCs!
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re passionate about IP design and how your background makes you a perfect fit for our team. We love seeing enthusiasm and a bit of personality, so let us know what excites you about this opportunity.
Showcase Your Collaboration Skills: Since this role involves working closely with various teams, make sure to mention any collaborative projects you've been part of. We value teamwork, so highlight your ability to work with cross-functional teams and how you’ve contributed to successful outcomes.
Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it gives you a chance to explore more about StudySmarter and what we stand for!
How to prepare for a job interview at Stackstudio Digital Ltd.
✨Know Your RTL Inside Out
Make sure you brush up on your SystemVerilog skills. Be ready to discuss your past projects where you've developed RTL for FPGA or Adaptive SoC designs. Highlight specific challenges you faced and how you overcame them.
✨Familiarise Yourself with High-Speed Protocols
Since the role requires experience with protocols like 100Gb Ethernet and PCIe Gen5, it’s crucial to understand these technologies. Prepare to explain how you've implemented these protocols in previous roles and any optimisations you made.
✨Show Off Your Collaboration Skills
This position involves working closely with various teams. Think of examples where you successfully collaborated with architecture, verification, or integration teams. Be ready to discuss how you handled conflicts or differing opinions.
✨Demonstrate Your Scripting Savvy
Proficiency in scripting is a must. Prepare to talk about your experience with Python and Tcl, especially in automating workflows. If you have examples of scripts you've written that improved processes, be sure to mention those!
