DV Engineer

Role – DV Engineer Location: EU / Remote

Mandatory Skill:

• IP/ SOC verification
• Verilog, System Verilog, UVM
• Code Coverage, functional coverage

Industry Experience : 5 to 10 years

• SOC Verfication Experience on ARM Ecosystem
• PCIE Experience and also PCIE-VIP usage experience
• GLS working experience
• Proficient in C/System Verilog and UVM
• Working knowledge of GIT

Soft skill – Good Communication and willingness to learn

JBRP1_UKTJ