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- Tasks: Design high-performance IP for next-gen FPGA/Adaptive SoC technologies.
- Company: Join Tata Consultancy Services, a leader in tech transformation.
- Benefits: Remote work, diverse environment, and opportunities for professional growth.
- Why this job: Shape the future of technology while collaborating with top engineering teams.
- Qualifications: Expertise in System Verilog RTL and FPGA design flow required.
- Other info: 6-month contract with potential for extension based on performance.
The predicted salary is between 36000 - 60000 £ per year.
Location: Belfast, UK (Remote)
Job Type: Contract (Inside IR35)
Duration: 6 months, with the potential for extension based on project needs and performance
Job Summary: Join Tata Consultancy Services (TCS) as a Senior IP Design Engineer and play a key role in designing high-performance IP for next-generation FPGA/Adaptive SoC technologies. Work remotely on impactful projects that help shape the future of FPGA and SoC design, collaborating with top-tier engineering teams and expanding your technical horizons.
About the Company: TCS is a leading transformation company partnering with some of the world's biggest brands. At TCS, you'll be part of innovative, challenging projects that drive real impact and support your professional growth in a diverse, inclusive environment.
Key Responsibilities:
- Design high-performance IP targeting FPGA/Adaptive SoC technology using System Verilog RTL.
- Deliver synthesis-ready designs that meet timing and integration requirements.
- Collaborate with engineering teams to ensure quality and performance targets are met.
Skills, Experience, and Abilities Required:
- Expertise in System Verilog RTL design
- Hands-on experience with 100Gb Ethernet, PCIe Gen5, AMBA/AXI
- In-depth knowledge of FPGA/Adaptive SoC design flow, including place & route (P&R) and timing closure
- Proficiency in Vivado/Vitis
- Strong scripting skills in Python and Tcl
- Experience with Git and CI/CD
Additional Information:
Remote role: No regular office attendance required.
Senior IP Design Engineer in Bristol employer: Stackstudio Digital Ltd.
Contact Detail:
Stackstudio Digital Ltd. Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Senior IP Design Engineer in Bristol
✨Tip Number 1
Network like a pro! Reach out to your connections in the industry, especially those who work at TCS or similar companies. A friendly chat can sometimes lead to opportunities that aren’t even advertised.
✨Tip Number 2
Show off your skills! Create a portfolio showcasing your best projects, especially those involving System Verilog RTL and FPGA design. This will give potential employers a clear view of what you can bring to the table.
✨Tip Number 3
Prepare for interviews by brushing up on common technical questions related to FPGA/Adaptive SoC design. Practice explaining your thought process clearly, as communication is key in collaborative environments.
✨Tip Number 4
Don’t forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, we love seeing candidates who take the initiative to connect directly with us.
We think you need these skills to ace Senior IP Design Engineer in Bristol
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your expertise in System Verilog RTL design and any hands-on experience with 100Gb Ethernet or PCIe Gen5. We want to see how your skills align with the role, so don’t be shy about showcasing relevant projects!
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re passionate about FPGA/Adaptive SoC technologies and how your background makes you a perfect fit for our team. Keep it engaging and personal – we love to see your personality!
Show Off Your Technical Skills: When detailing your experience, be specific about your proficiency in tools like Vivado/Vitis and your scripting skills in Python and Tcl. We’re looking for candidates who can hit the ground running, so make sure we know what you bring to the table!
Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it’s super easy – just follow the prompts and let us know you’re interested!
How to prepare for a job interview at Stackstudio Digital Ltd.
✨Know Your Tech Inside Out
Make sure you brush up on your System Verilog RTL design skills and be ready to discuss your hands-on experience with 100Gb Ethernet, PCIe Gen5, and AMBA/AXI. Prepare to explain how you've tackled timing closure and integration challenges in past projects.
✨Showcase Your Collaboration Skills
Since the role involves working closely with engineering teams, think of examples where you've successfully collaborated on projects. Be ready to share how you ensured quality and performance targets were met while working with others.
✨Demonstrate Your Scripting Savvy
Highlight your proficiency in Python and Tcl during the interview. You might be asked to solve a problem or explain how you've used scripting to automate tasks in your previous roles, so have some examples ready.
✨Familiarise Yourself with Tools
Get comfortable with Vivado/Vitis and Git, as these are crucial for the role. If you can, try to bring up specific instances where you've used these tools effectively, especially in CI/CD environments, to show your practical knowledge.
