A leading technology company in the United Kingdom is seeking a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog methodologies. The role includes responsibilities such as developing UVM-based verification environments, integrating verification IP for cutting-edge protocols, and automating verification flows using Python. Strong experience in verification environments and knowledge of protocols like 100Gb Ethernet and PCIe Gen5 is essential for success in this position. #J-18808-Ljbffr
Contact Detail:
SRMD Ltd. Recruiting Team