Design Engineer in Oxford

Design Engineer in Oxford

Oxford Full-Time 36000 - 60000 £ / year (est.) No home office possible
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At a Glance

  • Tasks: Lead verification of RF/DSP signal-chain blocks and develop UVM testbenches.
  • Company: Join a cutting-edge tech firm focused on innovative signal processing solutions.
  • Benefits: Attractive salary, flexible working options, and opportunities for professional growth.
  • Why this job: Make a real impact in the world of RF/DSP technology and work with top experts.
  • Qualifications: Experience with UVM, SystemVerilog, and DSP verification is essential.
  • Other info: Dynamic team environment with excellent career advancement potential.

The predicted salary is between 36000 - 60000 £ per year.

We are seeking a Senior Verification Engineer with strong expertise in RF/DSP signal-chain verification. The role focuses on driving end-to-end verification of complex DSP and RF blocks using UVM-based methodologies and advanced verification techniques. You will work closely with design and algorithm teams to validate signal-processing functionality and ensure high-quality silicon.

Key Responsibilities:

  • Lead verification of RF/DSP signal-chain blocks using UVM
  • Develop and maintain UVM testbenches and integrate VIPs
  • Verify DSP algorithms such as FFT, FIR filters, and channelizers
  • Create Python-based verification utilities and support CI/CD flows
  • Collaborate with design and system teams to debug and close coverage

Required Skills & Experience:

  • Strong hands-on experience with UVM and SystemVerilog
  • Proven DSP verification experience (FFT, FIR, channelizers)
  • Proficiency in Python scripting and CI/CD environments
  • Experience with verification planning, coverage, and debug

Preferred Qualifications:

  • MATLAB experience for algorithm modeling and validation

Design Engineer in Oxford employer: SRMD Ltd.

As a leading employer in the technology sector, we offer a dynamic work environment that fosters innovation and collaboration. Our commitment to employee growth is evident through continuous training opportunities and a culture that encourages creative problem-solving. Located in a vibrant tech hub, we provide competitive benefits and a supportive atmosphere where your contributions directly impact cutting-edge projects in RF and DSP verification.
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Contact Detail:

SRMD Ltd. Recruiting Team

StudySmarter Expert Advice 🤫

We think this is how you could land Design Engineer in Oxford

✨Tip Number 1

Network like a pro! Reach out to folks in the industry, attend meetups, and connect with people on LinkedIn. You never know who might have the inside scoop on job openings or can refer you directly.

✨Tip Number 2

Show off your skills! Create a portfolio showcasing your projects, especially those involving UVM and DSP verification. This gives potential employers a taste of what you can do and sets you apart from the crowd.

✨Tip Number 3

Prepare for interviews by brushing up on your technical knowledge. Be ready to discuss your experience with UVM, SystemVerilog, and Python scripting. Practising common interview questions can help you feel more confident.

✨Tip Number 4

Don’t forget to apply through our website! We’ve got loads of opportunities waiting for talented individuals like you. Plus, it’s a great way to ensure your application gets seen by the right people.

We think you need these skills to ace Design Engineer in Oxford

RF/DSP Signal-Chain Verification
UVM
SystemVerilog
DSP Verification
FFT
FIR Filters
Channelizers
Python Scripting
CI/CD Environments
Verification Planning
Coverage Analysis
Debugging Skills
MATLAB

Some tips for your application 🫡

Tailor Your CV: Make sure your CV highlights your experience with UVM and DSP verification. We want to see how your skills match the job description, so don’t be shy about showcasing relevant projects or achievements!

Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re passionate about RF/DSP verification and how your background makes you a perfect fit for our team. Keep it engaging and personal!

Show Off Your Technical Skills: Don’t forget to mention your proficiency in Python scripting and CI/CD environments. We love seeing candidates who can bring technical expertise to the table, so make sure to highlight any relevant experience.

Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it’s super easy!

How to prepare for a job interview at SRMD Ltd.

✨Know Your UVM Inside Out

Make sure you brush up on your UVM and SystemVerilog knowledge. Be prepared to discuss how you've used these methodologies in past projects, and think of specific examples where you led verification efforts. This will show that you’re not just familiar with the tools, but that you can apply them effectively.

✨Show Off Your DSP Skills

Since the role focuses on DSP verification, be ready to dive deep into your experience with algorithms like FFT and FIR filters. Prepare to explain how you’ve validated these in previous roles, and if possible, bring along any relevant projects or results to showcase your expertise.

✨Python Proficiency is Key

As Python scripting is a requirement, make sure you can talk about your experience with it confidently. Think of examples where you've created verification utilities or supported CI/CD flows using Python. If you have any cool scripts or tools you've developed, don’t hesitate to mention them!

✨Collaboration is Crucial

This role involves working closely with design and algorithm teams, so be prepared to discuss your teamwork experiences. Share examples of how you’ve collaborated to debug issues or close coverage gaps. Highlighting your communication skills will show that you can work well in a team environment.

Design Engineer in Oxford
SRMD Ltd.
Location: Oxford
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  • Design Engineer in Oxford

    Oxford
    Full-Time
    36000 - 60000 £ / year (est.)
  • S

    SRMD Ltd.

    50-100
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