Lead Verification Engineer – High-Speed Networking & VIP

A leading tech company in Scotland is seeking a Senior Verification Engineer to verify high-speed networking IP. The ideal candidate will develop UVM-based verification environments and utilize advanced SystemVerilog methodologies. Responsibilities include automated verification using Python and integrating verification IP for protocols like 100Gb Ethernet and PCIe Gen5. Strong knowledge of associated tools like Vivado and CI/CD environments is required. #J-18808-Ljbffr