SENIOR PRINCIPAL SOC IP DESIGN VERIFICATION ENGINEER - CAMBRIDGE- ENG
SENIOR PRINCIPAL SOC IP DESIGN VERIFICATION ENGINEER - CAMBRIDGE- ENG

SENIOR PRINCIPAL SOC IP DESIGN VERIFICATION ENGINEER - CAMBRIDGE- ENG

Cambridge Full-Time 72000 - 108000 £ / year (est.) No home office possible
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At a Glance

  • Tasks: Develop and validate cutting-edge SoC reference systems for high-performance applications.
  • Company: Join a leading multinational semiconductor organisation shaping the future of technology.
  • Benefits: Enjoy competitive salary, remote work options, and opportunities for professional growth.
  • Why this job: Be part of a dynamic team with high visibility and impact in the tech industry.
  • Qualifications: 8+ years experience in ASIC design; expertise in Verilog/System Verilog required.
  • Other info: Work on innovative projects in areas like AI, automotive, and machine learning.

The predicted salary is between 72000 - 108000 £ per year.

Client:

Our client a leading Multinational Semiconductor Organisation requires Senior Principal SoC IP Design Verification Engineer for role based in Cambridge, England.

Role:

The group develops and licenses IP for system designs. This includes CPUs and high-performance DSPs, DDR and IO controllers, hardware accelerators, and subsystems. The IP designs are used by most of the top semiconductor vendors today, and our customers are shipping billions of chips annually using our components.

The Engineering team seeks an experienced and talented SoC design verification engineer. In this role, you will be responsible for developing and validating reference systems for Computer Vision, Machine Learning, Radar, Automotive, and other high-performance applications.

This is a technically rewarding role with high visibility within the organisation. The group will also implement reference designs on emulation systems and support applications for product demonstrations.

This role requires extensive experience IP integration and implementing SoC and compute-based systems. You will work closely with compute and interface IP development engineering and build designs to demonstrate the capabilities ofsubsystems and components.

Responsibilities:

  • Develop, implement, and debug SoC reference systems.
  • Integrate compute, memory and interface IP in system designs.
  • Analyse IP products and implementation flows.
  • Identify gaps and work with development teams to improve products.
  • Develop collateral, and training material for CSG system customers.
  • Identify and implement best practices in hardware design, testing, and validation to improve efficiency and reliability.
  • Stay up to date with latest industry trends, technologies, and design methodologies, and incorporate them into team’s workflows.

Education:

  • BS in Electronic Engineering/Computer Science

Experience:

  • 8+ years work experience
  • Must have at least 3 years of experience in ASIC design, integration, or verification.
  • Must have expertise in some of the following domains: processor design, on-chip communication and interconnects, high-speed interfaces, or chiplets.
  • Expertise in Verilog/System Verilog for coding and verification.
  • Proficiency in RTL design techniques, including synthesis, timing closure, and verification.
  • Experience in using UVM for functional verification of ASIC designs.
  • Experience with EDA tools like Cadence and Synopsys for design simulation and verification.
  • Extensive experience with FPGA emulation, design tools, and verification.

Contact:
For further information please contact Mícheál at Software Placements on 00353 1 5254642 or email #J-18808-Ljbffr

SENIOR PRINCIPAL SOC IP DESIGN VERIFICATION ENGINEER - CAMBRIDGE- ENG employer: Software Placements

Our client is a leading multinational semiconductor organisation that offers an exceptional work environment in Cambridge, England. With a strong focus on innovation and cutting-edge technology, employees benefit from a collaborative culture that encourages professional growth and development. The company provides competitive compensation, comprehensive benefits, and the opportunity to work on high-impact projects that shape the future of technology.
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Contact Detail:

Software Placements Recruiting Team

StudySmarter Expert Advice 🤫

We think this is how you could land SENIOR PRINCIPAL SOC IP DESIGN VERIFICATION ENGINEER - CAMBRIDGE- ENG

✨Tip Number 1

Network with professionals in the semiconductor industry, especially those who work in SoC design and verification. Attend relevant conferences or meetups in Cambridge to connect with potential colleagues and learn about the latest trends.

✨Tip Number 2

Showcase your expertise in Verilog/System Verilog and UVM by contributing to open-source projects or writing articles on platforms like LinkedIn. This will demonstrate your knowledge and passion for the field to potential employers.

✨Tip Number 3

Familiarise yourself with the specific EDA tools mentioned in the job description, such as Cadence and Synopsys. Consider taking online courses or tutorials to enhance your skills and make yourself a more attractive candidate.

✨Tip Number 4

Prepare to discuss your previous experience with ASIC design and verification during interviews. Be ready to provide examples of how you've integrated compute and interface IP in system designs, as this will be crucial for the role.

We think you need these skills to ace SENIOR PRINCIPAL SOC IP DESIGN VERIFICATION ENGINEER - CAMBRIDGE- ENG

ASIC Design
IP Integration
SoC Design Verification
Verilog/System Verilog
UVM for Functional Verification
RTL Design Techniques
Synthesis and Timing Closure
EDA Tools (Cadence, Synopsys)
FPGA Emulation
High-Speed Interfaces
On-Chip Communication and Interconnects
Chiplets Design
Debugging Skills
Analytical Skills
Collaboration and Teamwork
Industry Trend Awareness

Some tips for your application 🫡

Tailor Your CV: Make sure your CV highlights relevant experience in ASIC design, integration, and verification. Emphasise your expertise in Verilog/System Verilog and any specific projects that relate to the role.

Craft a Strong Cover Letter: Write a cover letter that clearly outlines your passion for SoC design verification and how your background aligns with the responsibilities listed in the job description. Mention specific technologies or methodologies you have worked with.

Showcase Relevant Projects: Include details of any significant projects you've worked on that demonstrate your skills in developing and validating reference systems, especially in areas like Computer Vision or Machine Learning.

Highlight Continuous Learning: Mention any recent courses, certifications, or industry trends you are following that relate to the semiconductor field. This shows your commitment to staying updated and improving your skills.

How to prepare for a job interview at Software Placements

✨Showcase Your Technical Expertise

Make sure to highlight your extensive experience in ASIC design, integration, and verification. Be prepared to discuss specific projects where you've successfully implemented SoC reference systems or worked with high-speed interfaces.

✨Demonstrate Problem-Solving Skills

Prepare examples of how you've identified gaps in IP products and collaborated with development teams to improve them. This will show your proactive approach and ability to work effectively within a team.

✨Familiarise Yourself with Industry Trends

Stay updated on the latest technologies and methodologies in the semiconductor industry. Being able to discuss recent advancements or trends during the interview will demonstrate your passion and commitment to the field.

✨Prepare for Technical Questions

Expect in-depth technical questions related to Verilog/System Verilog, UVM, and EDA tools like Cadence and Synopsys. Brush up on these topics and be ready to explain your thought process and problem-solving techniques.

SENIOR PRINCIPAL SOC IP DESIGN VERIFICATION ENGINEER - CAMBRIDGE- ENG
Software Placements
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  • SENIOR PRINCIPAL SOC IP DESIGN VERIFICATION ENGINEER - CAMBRIDGE- ENG

    Cambridge
    Full-Time
    72000 - 108000 £ / year (est.)

    Application deadline: 2027-08-08

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    Software Placements

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