Principal Verification Engineer

Principal Verification Engineer Salary: £100,000 – £130,000 Location: Bristol Working Env: Hybrid preferred, but can be flexible   The company is a UK-based tech firm operating at the bleeding edge of secure computing, engineering security & encryption accelerator cards with the ability to securely process data at high speeds whilst ensuring it remains encrypted throughout.   Following a sizeable funding round, they are building out upon the foundations of their verification team and looking for a Principal Verification Engineer to join the team.   As a Principal Verification Engineer, you will be joining a flat-structured team and working across the entire verification flow of both block-level and system-level designs (RTL logic & Integration with external IP) within a UVM environment. This is a hands-on role granting you ownership and autonomy to technically lead the tasks you take on.   Key Requirements: Excellent command of SystemVerilog. Experience of technical leadership and exposure to working across the full verification life cycle, from planning & architecture through to assertions and coverage. Experience working within a UVM environment Experience of SoC-level and/or block-level verification  Desired, but not essential: Experience of scripting, HW design and/or low-level software engineering. Experience of formal verification. Experience working on the verification of HW accelerators or other processing units