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For Companies At a Glance
- Tasks: Lead verification tasks in a hands-on role, ensuring high-speed secure data processing.
- Company: Join a cutting-edge UK tech firm specialising in secure computing and encryption technology.
- Benefits: Enjoy a hybrid working environment with flexibility and competitive salary.
- Why this job: Be part of a flat-structured team, driving innovation in secure data processing.
- Qualifications: Strong SystemVerilog skills and experience in full verification life cycle required.
- Other info: Opportunity to work on advanced hardware accelerators and gain technical leadership experience.
The predicted salary is between 80000 - 120000 £ per year.
The company is a UK-based tech firm operating at the bleeding edge of secure computing, engineering security & encryption accelerator cards with the ability to securely process data at high speeds whilst ensuring it remains encrypted throughout. Following a sizeable funding round, they are building out upon the foundations of their verification team and looking for a Principal Verification Engineer to join the team.
As a Principal Verification Engineer, you will be joining a flat-structured team and working across the entire verification flow of both block-level and system-level designs (RTL logic & Integration with external IP) within a UVM environment. This is a hands-on role granting you ownership and autonomy to technically lead the tasks you take on.
Key Requirements:
- Excellent command of SystemVerilog.
- Experience of technical leadership and exposure to working across the full verification life cycle, from planning & architecture through to assertions and coverage.
- Experience working within a UVM environment.
- Experience of SoC-level and/or block-level verification.
Desired, but not essential:
- Experience of scripting, HW design and/or low-level software engineering.
- Experience of formal verification.
- Experience working on the verification of HW accelerators or other processing units.
Principal Verification Engineer employer: So Code Limited
Contact Detail:
So Code Limited Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Principal Verification Engineer
✨Tip Number 1
Make sure to brush up on your SystemVerilog skills. Since this role requires an excellent command of SystemVerilog, being able to demonstrate your proficiency during discussions or interviews will set you apart from other candidates.
✨Tip Number 2
Familiarise yourself with the UVM environment. Since you'll be working in a UVM setting, having hands-on experience or knowledge about UVM methodologies can help you speak confidently about your past projects and how they relate to this role.
✨Tip Number 3
Prepare to discuss your technical leadership experiences. This position involves leading tasks, so think of specific examples where you've successfully led a project or team, and be ready to share these stories during your interview.
✨Tip Number 4
Network with professionals in the field. Engaging with others who work in verification engineering can provide insights into the company culture and expectations, plus it might even lead to a referral, which can significantly boost your chances of landing the job.
We think you need these skills to ace Principal Verification Engineer
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your experience with SystemVerilog and UVM environments. Emphasise any technical leadership roles you've held and detail your involvement in the full verification life cycle.
Craft a Compelling Cover Letter: In your cover letter, explain why you're interested in the Principal Verification Engineer position. Mention specific projects or experiences that demonstrate your expertise in SoC-level and block-level verification.
Showcase Relevant Skills: When detailing your skills, focus on those mentioned in the job description, such as scripting, hardware design, and formal verification. Provide examples of how you've applied these skills in previous roles.
Proofread Your Application: Before submitting, carefully proofread your application for any spelling or grammatical errors. A polished application reflects your attention to detail, which is crucial for a role in verification engineering.
How to prepare for a job interview at So Code Limited
✨Showcase Your Technical Expertise
Be prepared to discuss your command of SystemVerilog and your experience with UVM environments. Bring examples of past projects where you led verification tasks, highlighting your technical leadership and problem-solving skills.
✨Understand the Company’s Focus
Research the company’s work in secure computing and encryption accelerator cards. Demonstrating knowledge about their products and how your skills align with their goals will show your genuine interest in the role.
✨Prepare for Scenario-Based Questions
Expect questions that assess your approach to the full verification life cycle. Be ready to explain how you would handle specific challenges in planning, architecture, assertions, and coverage in a verification project.
✨Emphasise Your Hands-On Experience
Since this is a hands-on role, share specific instances where you took ownership of verification tasks. Discuss how you managed your responsibilities and the impact of your contributions on the team’s success.
