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- Tasks: Join a team of engineers to design next-gen GPUs, handling the full implementation flow.
- Company: Work with a prestigious name in the semiconductor industry, known for innovation.
- Benefits: Enjoy a hybrid working environment and competitive daily rates.
- Why this job: Be part of cutting-edge technology and collaborate with top professionals in the field.
- Qualifications: 8+ years in Physical Design, experience with Cadence and Synopsys tools required.
- Other info: Initial 6-month contract with potential for extension.
INSIDE OF IR35 CONTRACT – Physical Design Engineer
Contract Length: 6 Months (possibility for extension)
Rate: £600 – £800 per day
Location: Cambridgeshire
Working Env: Hybrid (2 days on-site)
This is an opportunity to join one of the most prestigious names in the semiconductor industry on an initial 6-month contract, working within a team of 6 engineers on the next generation of GPUs.
As a Physical Design Engineer, you will be working across the entire implementation flow cycle from RTL Synthesis through place and route, to STA, including LEC and CLP checks. You will provide regular detailed feedback and work closely with the RTL Designers to improve PPA and remove implementation bottlenecks, whilst also collaborating with EDA vendors to solve tool issues and advance PPA.
Key Requirements:
- 8+ years of experience within Physical Design, ideally with exposure to low-power design techniques.
- Experience with Cadence (Genus, Innovus, Tempus, QRC, Conformal) and Synopsys (Fusion Compiler, Formality) tools.
- Understanding in building flows and methodology using scripting languages such as TCL, Python, Perl to support project development.
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ASIC Physical Design Engineer employer: So Code Limited
Contact Detail:
So Code Limited Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land ASIC Physical Design Engineer
✨Tip Number 1
Network with professionals in the semiconductor industry, especially those who work in physical design. Attend relevant meetups or webinars to connect with potential colleagues and learn about their experiences.
✨Tip Number 2
Familiarise yourself with the latest trends and technologies in ASIC design, particularly low-power techniques. This knowledge can help you stand out during discussions with hiring managers.
✨Tip Number 3
Engage with EDA tool communities online, such as forums or social media groups. Sharing insights and asking questions can demonstrate your enthusiasm and expertise in tools like Cadence and Synopsys.
✨Tip Number 4
Prepare to discuss specific projects where you've successfully improved PPA or resolved implementation bottlenecks. Real-world examples will showcase your problem-solving skills and experience effectively.
We think you need these skills to ace ASIC Physical Design Engineer
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your 8+ years of experience in Physical Design. Emphasise your familiarity with low-power design techniques and the specific tools mentioned in the job description, such as Cadence and Synopsys.
Craft a Strong Cover Letter: Write a cover letter that showcases your understanding of the role and how your skills align with the requirements. Mention your experience with RTL Synthesis, place and route, and your ability to collaborate with RTL Designers and EDA vendors.
Showcase Relevant Projects: Include specific examples of projects where you have successfully implemented flows and methodologies using scripting languages like TCL, Python, or Perl. This will demonstrate your hands-on experience and problem-solving abilities.
Proofread Your Application: Before submitting, carefully proofread your application for any spelling or grammatical errors. A polished application reflects your attention to detail, which is crucial in the semiconductor industry.
How to prepare for a job interview at So Code Limited
✨Showcase Your Technical Expertise
Make sure to highlight your 8+ years of experience in Physical Design. Be prepared to discuss specific projects where you used tools like Cadence and Synopsys, and how you tackled challenges related to low-power design techniques.
✨Demonstrate Collaboration Skills
Since the role involves working closely with RTL Designers and EDA vendors, be ready to share examples of how you've successfully collaborated in past projects. Emphasise your ability to provide constructive feedback and solve issues as a team.
✨Prepare for Technical Questions
Expect in-depth technical questions about the implementation flow cycle, including RTL Synthesis, place and route, and STA. Brush up on your knowledge of LEC and CLP checks, and be ready to explain how you've applied these in your previous roles.
✨Familiarise Yourself with Scripting Languages
Since building flows and methodologies using scripting languages is crucial for this position, make sure you can discuss your experience with TCL, Python, or Perl. Prepare to talk about how you've used these languages to support project development.