SiFive is seeking a qualified engineer to architect, design, and implement features and ISA extensions in RISC-V CPU core generators using Chisel. You will integrate content into the FIRRTL framework and help automate documentation, verification tests, and packaged software. You will verify designs with the verification team and work with physical implementation to optimize for frequency, area, and power. The role requires 3+ years of design experience, proficiency in Verilog/SystemVerilog/VHDL, #J-18808-Ljbffr
Senior RTL Design Engineer — RISC-V Core Architect employer: SiFive
SiFive is an exceptional employer, renowned for its commitment to innovation and collaboration in the technology sector. Located in the vibrant city of Cambridge, employees benefit from a dynamic work culture that fosters creativity and teamwork, alongside opportunities for professional growth in cutting-edge CPU design. With a focus on diversity and inclusion, SiFive not only champions groundbreaking ideas but also supports its talented workforce in achieving their career aspirations.
