SiFive is hiring a CPU Microarchitecture/RTL design engineer to join a team delivering industry‑leading CPU cores based on the open‑source RISC‑V architecture. You will design features, extend ISA, and integrate content into Chisel/FIRRTL while coordinating with verification and physical teams. You will contribute to documentation, improve testbenches, and drive performance exploration to meet aggressive goals in a fast‑paced environment. #J-18808-Ljbffr
Senior RISC-V RTL Design Engineer (Microarchitecture) employer: SiFive
SiFive is an exceptional employer, renowned for its commitment to innovation and collaboration in the technology sector. Located in the vibrant city of Cambridge, employees benefit from a dynamic work culture that fosters creativity and teamwork, alongside opportunities for professional growth in cutting-edge CPU design. With a focus on diversity and inclusion, SiFive not only champions groundbreaking ideas but also supports its talented workforce in achieving their career aspirations.
