RISC-V Debug, Trace & Profiling IP Architect

RISC-V Debug, Trace & Profiling IP Architect

Full-Time On-site
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SiFive is seeking a hardware design engineer in Cambridge with a passion for developing advanced debug, trace, and profiling hardware. This role involves collaborating with cross-functional teams to design high-performance hardware that supports RISC-V architecture. The ideal candidate will have over 7 years of experience in RTL design, strong proficiency in Verilog or VHDL, and a Master's or PhD in a related field. SiFive promotes diversity and an inclusive work environment. #J-18808-Ljbffr

RISC-V Debug, Trace & Profiling IP Architect employer: SiFive

SiFive is an exceptional employer, renowned for its commitment to innovation and collaboration in the technology sector. Located in the vibrant city of Cambridge, employees benefit from a dynamic work culture that fosters creativity and teamwork, alongside opportunities for professional growth in cutting-edge CPU design. With a focus on diversity and inclusion, SiFive not only champions groundbreaking ideas but also supports its talented workforce in achieving their career aspirations.

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Contact Details:

SiFive Recruitment Team