At a Glance
- Tasks: Design cutting-edge CPU and interconnect IP, driving RISC-V adoption.
- Company: Join SiFive, a leader in innovative hardware engineering.
- Benefits: Competitive salary, flexible work options, and growth opportunities.
- Other info: Dynamic team environment with a focus on innovation and quality.
- Why this job: Be at the forefront of technology and make a real impact in the industry.
- Qualifications: Experience in hardware design and strong collaboration skills.
The predicted salary is between 70000 - 100000 £ per year.
SiFive is seeking a principal‑level hardware engineer to design industry‑leading CPU and interconnect IP, driving RISC‑V adoption across SOC designs. You will build highly configurable hardware generators using Chisel/Scala and integrate them into SiFive’s Chisel/FIRRTL workflow. The role emphasizes scalable IP design, fast time‑to‑market, and collaboration across verification and design teams to deliver high‑quality, performant solutions.
Principal Interconnect IP Design Engineer (RISC‑V/TileLink) employer: SiFive
SiFive is an exceptional employer that fosters a culture of innovation and collaboration, making it an ideal place for talented engineers to thrive. With a focus on cutting-edge technology and RISC-V adoption, employees benefit from continuous growth opportunities and the chance to work on impactful projects in a dynamic environment. Located in a vibrant tech hub, SiFive offers a supportive atmosphere where creativity and teamwork are highly valued.
