Principal Interconnect Design Engineer

About SiFive

As the pioneers who introduced RISC‑V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC‑V to the highest performance and most data‑intensive applications. SiFive’s compute platforms enable leading technology companies to innovate and deliver advanced solutions across artificial intelligence, machine learning, automotive, data centre, mobile, and consumer chip design. With SiFive, the future of RISC‑V has no limits. SiFive is excited to connect with talented individuals who share our passion for driving innovation and changing the world. Our teams collaborate to create groundbreaking ideas that have a huge impact on people’s lives, making the world a better place, one processor at a time.

The Role

SiFive is looking for a principal‑level hardware engineer to design industry‑leading CPU and interconnect IP, driving the adoption of RISC‑V as the architecture of choice for SOC designs across a broad range of vertical applications. The role focuses on massively customizable IP and improving time‑to‑market by designing hardware as highly‑configurable generators using the Chisel hardware construction language embedded in Scala.

The Challenge

• Design the best interconnect IP in the world using the revolutionary open RISC‑V and TileLink architectures.
• Master the art of designing hardware as configurable generators in a domain‑specific software language for elaborating circuits.
• Work in a fast‑paced, dynamic environment to bring new hardware IP to market quickly with high quality and exceptional performance.

Responsibilities

• Architect, design, and implement an enhanced TileLink interconnect, cache controllers, protocol bridges, and other infrastructure/uncore logic as RTL generators in Chisel.
• Implement RTL generators so elements self‑configure to optimally connect to each other.
• Enhance future designs to provide higher performance, more efficient multicore and multisystem coherence.
• Design extensive configurability as a first‑class consideration.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements that enable automatic configuration, generation of documentation, verification testbenches, and packaged software.
• Perform initial sandbox verification and collaborate with the design verification team to create and execute thorough verification test plans.
• Ensure knowledge sharing through creation and maintenance of great documentation and participation in a culture of collaborative design.

What You Bring To The Challenge

• Knowledge of cache and cache coherency architectures and concepts.
• Experience with NoC or other interconnect fabrics.
• Familiarity with industry‑standard bus protocols (AXI, AHB, APB, CHI, CXL, UCIe).
• Ability to architect solutions to connect bus fabrics of disparate protocols.
• Strong software engineering skills, including: Object‑oriented, aspect‑oriented, and particularly functional programming.
• Templated metaprogramming in any language.
• Compiler infrastructures, particularly for domain‑specific languages.
• Data modeling, especially intermediate representations for optimizing or transforming compiler passes.
• Test‑driven development and ability to write adaptive unit tests.
• Proficiency in hardware (RTL) design in Verilog, SystemVerilog, or VHDL.
• Attention to detail and focus on high‑quality design.
• Team‑player mindset and belief that engineering is a collective effort.
• BS/MS in EE, CE, CS or a related technical discipline, or equivalent experience.

Nice to Have

• Experience with Scala/Chisel, Bluespec, or another language/DSL for expressing configurable hardware via software.
• Knowledge of RISC‑V architecture.
• Experience with Git/GitHub, Jira, Confluence.