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- Tasks: Design and implement cutting-edge interconnect solutions for RISC-V architecture.
- Company: SiFive, a leader in innovative hardware design.
- Benefits: Competitive salary, flexible work options, and opportunities for professional growth.
- Other info: Collaborative culture with a focus on innovation and knowledge sharing.
- Why this job: Join a passionate team driving the future of CPU design with RISC-V technology.
- Qualifications: Experience in hardware design, software engineering, and interconnect architectures.
The predicted salary is between 60000 - 80000 ÂŁ per year.
SiFive is looking for a staff level hardware engineer who is passionate about designing industry‑leading CPU and interconnect IP to help drive the tidal wave of adoption of RISC‑V as the architecture of choice for SOC designs. We’re creating massively customizable IP and improving time‑to‑market by designing hardware as highly‑configurable generators. We leverage technology and ideas from the software industry to execute hardware design with the agility of software development.
Responsibilities
- Architect, design and implement an enhanced TileLink interconnect, cache controllers, protocol bridges, and other infrastructure/uncore logic as RTL generators in Chisel.
- Implement RTL generators such that elements self‑configure to optimally connect to each other.
- Enhance future designs to provide higher performance, more efficient multi‑core and multi‑system coherence.
- Design extensive configurability as a first‑class consideration.
- Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements that enable automatic configuration/generation of documentation, verification testbenches, and tests.
- Perform initial sandbox verification and work with the design verification team to create and execute thorough verification test plans.
- Ensure that knowledge is shared via creation and maintenance of great documentation and participation in a culture of collaborative design.
Qualifications
- Knowledge of cache and cache coherency architectures and concepts.
- Experience with NoC or other interconnect fabrics.
- Familiarity with industry‑standard bus protocols (AXI, AHB, APB, CHI).
- Ability to architect solutions to connect bus fabrics of disparate protocols.
- Strong software engineering skills/background, including: Object‑oriented, aspect‑oriented, and functional programming.
- Templated metaprogramming in any language.
- Compiler infrastructures, particularly for domain‑specific languages.
- Data modeling for intermediate representations that optimize or transform compiler passes.
- Test‑driven development and adaptive unit testing.
- Proficiency with hardware (RTL) design in Verilog, SystemVerilog, or VHDL.
- Attention to detail and a focus on high‑quality design.
- Ability to work well with others and belief that engineering is a team sport.
- BS/MS in EE, CE, CS or related technical discipline, or equivalent experience.
Nice to Have
- Experience with Scala/Chisel, Bluespec, or another DSL for expressing configurable hardware via software.
- Knowledge of RISC‑V architecture.
- Experience with Git, GitHub, Jira, Confluence.
Interconnect Design Engineer employer: SiFive
Contact Detail:
SiFive Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Interconnect Design Engineer
✨Tip Number 1
Network like a pro! Reach out to folks in the industry, attend meetups, and connect with current employees at SiFive. A friendly chat can sometimes lead to opportunities that aren’t even advertised!
✨Tip Number 2
Show off your skills! Create a portfolio showcasing your projects, especially those related to interconnect design or RISC-V architecture. This gives you a chance to demonstrate your expertise beyond just a CV.
✨Tip Number 3
Prepare for interviews by brushing up on relevant technologies and concepts. Be ready to discuss your experience with cache architectures and bus protocols, as these are key to the role at SiFive.
✨Tip Number 4
Don’t forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, it shows you’re genuinely interested in joining the SiFive team.
We think you need these skills to ace Interconnect Design Engineer
Some tips for your application 🫡
Tailor Your CV: Make sure your CV is tailored to the Interconnect Design Engineer role. Highlight your experience with cache architectures, interconnect fabrics, and any relevant programming skills. We want to see how your background aligns with our needs!
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Share your passion for RISC-V and how you can contribute to our mission at SiFive. Be sure to mention specific projects or experiences that showcase your skills in hardware design.
Showcase Your Team Spirit: At StudySmarter, we believe engineering is a team sport. In your application, emphasise your collaborative experiences and how you've worked with others to achieve great results. We love seeing candidates who value teamwork!
Apply Through Our Website: Don’t forget to apply through our website! It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it shows you’re serious about joining our team!
How to prepare for a job interview at SiFive
✨Know Your Stuff
Make sure you brush up on your knowledge of cache architectures and interconnect fabrics. Be ready to discuss industry-standard bus protocols like AXI and AHB, as well as your experience with RTL design in Verilog or SystemVerilog. The more you can demonstrate your expertise, the better!
✨Showcase Your Problem-Solving Skills
Prepare to talk about specific challenges you've faced in previous projects and how you architected solutions. Think about examples where you had to connect disparate bus fabrics or enhance performance in multi-core systems. Real-world examples will make your answers stand out.
✨Get Familiar with Chisel
Since SiFive is looking for someone who can integrate new design content into their Chisel/FIRRTL framework, it’s a good idea to familiarise yourself with these tools. If you have any experience with Scala or similar DSLs, be sure to highlight that during your interview.
✨Emphasise Teamwork
SiFive values collaboration, so be prepared to discuss how you’ve worked effectively in teams. Share examples of how you’ve contributed to a culture of collaborative design and how you ensure knowledge sharing through documentation and team interactions.