Staff RTL Design Engineer - CPU Midcore in Cambridge

About SiFive: As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications. SiFive’s compute platforms enable leading technology companies to innovate, optimize and deliver advanced solutions across chip design markets, including artificial intelligence, machine learning, automotive, data centre, mobile, and consumer.

The Role: As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team designing industry-leading CPU cores based on the open-source RISC-V architecture. We are looking for people who are excited to work in a fast-paced environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Responsibilities:

• Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to framework improvements to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
• Perform initial sandbox verification, and collaborate with the design verification team to create and execute thorough verification test plans.
• Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
• Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
• Microarchitecture development and specification. Share knowledge through documentation and participate in a culture of collaborative design.

Requirements:

• BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
• 5+ years of design experience.
• Academic or professional experience with CPU RTL design.
• Proficiency in hardware (RTL) design in Verilog, SystemVerilog, or VHDL.
• Strong software engineering skills/background, including:
• Object-oriented, aspect-oriented, and particularly functional programming
• Templated metaprogramming, in any language
• Compiler infrastructures, particularly for domain-specific languages
• Data modeling, particularly intermediate representations for optimizing or transforming compiler passes
• Test-driven development, particularly ability to write adaptive unit tests
• Attention to detail and a focus on high-quality design.
• Ability to work well with others and share the belief that engineering is teamwork.

Nice-to-haves:

• Experience with Scala/Chisel, Bluespec, or similar language/DSL for expressing configurable hardware via software.
• Knowledge of RISC-V architecture.
• Expertise in CPU processor designs in areas such as instruction decode; register renaming, reorder buffer, and instruction scheduling; vector units; load-store unit.
• Knowledge of verification principles, testbenches, UVM, and coverage.
• Experience with Git/GitHub, Jira, Confluence.

This position requires a successful background and reference checks and satisfactory proof of your right to work in the United Kingdom. Any offer of employment is contingent on verifying authorization for access to export-controlled technology under applicable export control laws or, if not authorized, our ability to obtain any necessary export licenses or approvals. SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.