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For Companies At a Glance
- Tasks: Design cutting-edge CPU cores using RISC-V architecture in a dynamic team environment.
- Company: Join SiFive, a leader in open-source hardware innovation.
- Benefits: Competitive salary, inclusive culture, and opportunities for professional growth.
- Other info: Collaborative atmosphere with a focus on teamwork and high-quality engineering.
- Why this job: Make a real impact in the tech world with revolutionary CPU designs.
- Qualifications: 3+ years in CPU RTL design; strong skills in Verilog or SystemVerilog.
The predicted salary is between 60000 - 80000 ÂŁ per year.
The Role
As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry‑leading CPU cores based on the revolutionary open‑source RISC‑V architecture. You will work in a fast‑paced, dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.
Responsibilities
- Architect, design, and implement new features, performance improvements, and ISA extensions in RISC‑V CPU core generators using Chisel.
- Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements that enable automatic configuration, documentation, verification testbenches, and packaged software.
- Perform initial sandbox verification and collaborate with the design verification team to create and execute thorough verification test plans.
- Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
- Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
- Develop microarchitecture specifications and share knowledge through excellent documentation and a culture of collaborative design.
Requirements
- BS/MS degree in computer science, computer engineering, electrical engineering, or a related field, or equivalent experience.
- 3+ years of design experience.
- Academic or professional experience with CPU RTL design.
- Proficiency in hardware (RTL) design in Verilog, SystemVerilog, or VHDL.
- Strong software engineering skills, including object‑oriented, aspect‑oriented, and functional programming, templated metaprogramming, compiler infrastructures for domain‑specific languages, data modeling for compiler passes, and test‑driven development with adaptive unit tests.
- Attention to detail and a focus on high‑quality design.
- Ability to work well with others and share the belief that engineering is teamwork.
Nice‑to‑haves
- Experience with Scala/Chisel, Bluespec, or other DSLs for configurable hardware.
- Knowledge of RISC‑V architecture.
- Expertise in CPU processor design areas such as instruction fetch, instruction decode, register renaming and instruction scheduling, vector units, or load‑store unit.
- Knowledge of verification principles, testbenches, UVM, and coverage.
- Experience with Git/GitHub, Jira, Confluence.
Additional Information
This position requires successful background and reference checks and satisfactory proof of your right to work in the United Kingdom. Any offer of employment is contingent on the Company verifying that you are authorized to access export‑controlled technology under applicable export control laws, or that the Company can obtain the necessary export licenses or approvals.
Equal Opportunity
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Senior RTL Design Engineer - CPU in Cambridge employer: SiFive
Contact Detail:
SiFive Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Senior RTL Design Engineer - CPU in Cambridge
✨Network Like a Pro
Get out there and connect with folks in the industry! Attend meetups, webinars, or even just grab a coffee with someone who works at SiFive. Building relationships can open doors that a CV just can't.
✨Show Off Your Skills
When you get the chance to chat with potential employers, don’t hold back! Share your projects, especially those involving CPU RTL design or RISC-V architecture. Let them see your passion and expertise in action.
✨Prepare for Technical Interviews
Brush up on your Verilog, SystemVerilog, and Chisel skills. Be ready to tackle some hands-on problems or case studies during interviews. Practice makes perfect, so consider mock interviews with friends or mentors.
✨Apply Through Our Website
Don’t forget to apply directly through our website! It’s the best way to ensure your application gets seen by the right people. Plus, it shows you’re genuinely interested in joining the SiFive team.
We think you need these skills to ace Senior RTL Design Engineer - CPU in Cambridge
Some tips for your application 🫡
Tailor Your CV: Make sure your CV is tailored to the role of Senior RTL Design Engineer. Highlight your experience with CPU RTL design and any relevant projects you've worked on, especially those involving RISC-V architecture.
Showcase Your Skills: Don’t just list your skills; demonstrate them! Use specific examples from your past work that showcase your proficiency in Verilog, SystemVerilog, or VHDL, and how you’ve applied these in real-world scenarios.
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Explain why you’re passionate about CPU design and how your background aligns with SiFive’s mission. Be sure to mention any experience with Chisel or similar tools.
Apply Through Our Website: We encourage you to apply through our website for a smoother application process. It helps us keep track of your application and ensures you don’t miss out on any important updates!
How to prepare for a job interview at SiFive
✨Know Your RISC-V Inside Out
Make sure you brush up on the RISC-V architecture and its nuances. Familiarise yourself with how it differs from other architectures, and be ready to discuss specific features or improvements you've worked on in your previous roles.
✨Showcase Your RTL Design Skills
Prepare to talk about your experience with RTL design using Verilog, SystemVerilog, or VHDL. Have examples ready that demonstrate your ability to architect and implement new features, and be prepared to dive into the details of your design process.
✨Collaboration is Key
Since teamwork is crucial in this role, think of examples where you've successfully collaborated with others. Be ready to discuss how you’ve worked with verification teams or physical implementation teams to achieve project goals.
✨Documentation Matters
Highlight your experience in creating clear and thorough documentation. Discuss how you ensure that your designs are well-documented and how you share knowledge within your team, as this will show your commitment to collaborative design.