Senior ALU Design Engineer in Cambridge

About SiFive

As the pioneers who introduced RISC‑V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC‑V to the highest performance and most data‑intensive applications in the world. SiFive’s unrivaled compute platforms enable leading technology companies to innovate, optimize and deliver the most advanced solutions across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC‑V has no limits. SiFive is excited to connect with talented individuals who are passionate about driving innovation and changing the world.

Job Description

As an Arithmetic RTL Design Engineer, you will be responsible for specifying, designing and implementing new arithmetic operators for RISC‑V instructions, optimizing timing, area, and power usage, and reducing latencies of existing operators. You will develop unit and formal tests, write new tests for new designs, work with the physical implementation team to optimize physical design for frequency, area, and power targets, and create high‑standard documentation that collaborates across teams and disciplines.

Responsibilities

• Specify, design and implement new arithmetic operators for arithmetic RISC‑V instructions, including floating‑point, vector, crypto and integer operations.
• Optimize timing, area and power usage, or reduce latencies of existing operators.
• Perform unit and formal testing for optimizations, writing new tests for new designs.
• Work with the physical implementation team to optimize physical design to frequency, area, and power targets.
• Create documentation to a high standard and collaborate across teams and disciplines.

Requirements

• Masters or higher degree in electronic engineering or computer science with a strong mathematical background, or a degree in a related field with a strong background in code development.
• 2+ years of RTL design or related design experience.
• Academic or professional experience with arithmetic RTL design or CPU RTL design in Chisel, Verilog, System Verilog or VHDL.
• Knowledge of at least one object‑oriented or functional programming language and willingness to adopt Chisel hardware generator design.
• Attention to detail and a focus on high‑quality code and documentation.
• Ability to work well with others and share the belief that engineering is teamwork.

This is a hybrid working position with 1 office day per week expected; more office days are possible if the successful candidate so prefers.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in the United Kingdom. Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export‑controlled technology under applicable export control laws or, if you are not already authorized, that the Company can successfully obtain any necessary export license(s) or other approvals.

Equal Opportunity

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.