At a Glance
- Tasks: Design advanced debug and profiling hardware for RISC-V architecture.
- Company: SiFive, a leader in innovative hardware design with a focus on inclusivity.
- Benefits: Competitive salary, diverse work culture, and opportunities for professional growth.
- Other info: Collaborative environment with a strong emphasis on diversity and inclusion.
- Why this job: Join a cutting-edge team and shape the future of hardware technology.
- Qualifications: 7+ years in RTL design, expertise in Verilog or VHDL, Master's or PhD required.
The predicted salary is between 60000 - 80000 £ per year.
SiFive is seeking a hardware design engineer in Cambridge with a passion for developing advanced debug, trace, and profiling hardware. This role involves collaborating with cross-functional teams to design high-performance hardware that supports RISC-V architecture.
The ideal candidate will have over 7 years of experience in RTL design, strong proficiency in Verilog or VHDL, and a Master's or PhD in a related field. SiFive promotes diversity and an inclusive work environment.
RISC-V Debug, Trace & Profiling IP Architect in Cambridge employer: SiFive
SiFive is an exceptional employer that fosters a culture of innovation and collaboration, making it an ideal place for talented engineers to thrive. With a focus on cutting-edge technology and RISC-V adoption, employees benefit from continuous growth opportunities and the chance to work on impactful projects in a dynamic environment. Located in a vibrant tech hub, SiFive offers a supportive atmosphere where creativity and teamwork are highly valued.
