At a Glance
- Tasks: Design cutting-edge CPU and interconnect IP, driving RISC-V adoption.
- Company: Join SiFive, a leader in innovative hardware engineering.
- Benefits: Competitive salary, flexible work options, and career advancement opportunities.
- Other info: Collaborative environment with a focus on high-quality, scalable solutions.
- Why this job: Be at the forefront of technology, shaping the future of SOC designs.
- Qualifications: Experience in hardware design and proficiency in Chisel/Scala.
The predicted salary is between 70000 - 90000 £ per year.
Si Five is seeking a principal‑level hardware engineer to design industry‑leading CPU and interconnect IP, driving RISC‑V adoption across SOC designs.
You will build highly configurable hardware generators using Chisel/Scala and integrate them into Si Five’s Chisel/FIRRTL workflow.
The role emphasizes scalable IP design, fast time‑to‑market, and collaboration across verification and design teams to deliver high‑quality, performant solutions.
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We think you need these skills to ace Principal Interconnect IP Design Engineer (RISC‑V/TileLink) in Cambridge
RISC-V
TileLink
Hardware Design
Chisel
Scala
IP Design
SOC Design
