At a Glance
- Tasks: Design cutting-edge CPU and interconnect IP, driving RISC-V adoption.
- Company: SiFive, a leader in hardware engineering and innovation.
- Benefits: Competitive salary, flexible work options, and opportunities for professional growth.
- Other info: Collaborative environment focused on delivering high-quality, scalable solutions.
- Why this job: Join a pioneering team and shape the future of technology with RISC-V.
- Qualifications: Experience in hardware design and proficiency in Chisel/Scala.
The predicted salary is between 70000 - 90000 £ per year.
Si Five is seeking a principal‐level hardware engineer to design industry‐leading CPU and interconnect IP, driving RISC‐V adoption across SOC designs.
You will build highly configurable hardware generators using Chisel/Scala and integrate them into Si Five's Chisel/FIRRTL workflow.
The role emphasizes scalable IP design, fast time‐to‐market, and collaboration across verification and design teams to deliver high‐quality, performant solutions. #J-18808-Ljbffr
Principal Interconnect IP Design Engineer (RISC‐V/TileLink) in Cambridge employer: SiFive
SiFive is an exceptional employer that fosters a culture of innovation and collaboration, making it an ideal place for talented engineers to thrive. With a focus on cutting-edge technology and RISC-V adoption, employees benefit from continuous growth opportunities and the chance to work on impactful projects in a dynamic environment. Located in a vibrant tech hub, SiFive offers a supportive atmosphere where creativity and teamwork are highly valued.
