SiFive is seeking a principal-level hardware engineer to drive the design of industry-leading CPU and interconnect IP for RISC-V SOCs. You will develop configurable hardware generators using Chisel and FIRRTL, enabling rapid, software-like iteration and high-quality hardware blocks.
Responsibilities include advancing TileLink interconnects, cache controllers and bridges, while ensuring high performance and scalable coherence across multi-core systems.
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Lead Interconnect Architect, RISC-V/TileLink (Chisel) in Cambridge employer: SiFive
SiFive is an exceptional employer, renowned for its commitment to innovation and collaboration in the technology sector. Located in the vibrant city of Cambridge, employees benefit from a dynamic work culture that fosters creativity and teamwork, alongside opportunities for professional growth in cutting-edge CPU design. With a focus on diversity and inclusion, SiFive not only champions groundbreaking ideas but also supports its talented workforce in achieving their career aspirations.
