At a Glance
- Tasks: Design and implement innovative features in RISC-V CPU cores using cutting-edge technologies.
- Company: Join SiFive, a leader in CPU design with a collaborative and inclusive culture.
- Benefits: Enjoy competitive salary, flexible work options, and opportunities for professional growth.
- Other info: Be part of a dynamic team that values collaboration and high-quality engineering.
- Why this job: Make a real impact in the tech world by working on groundbreaking CPU designs.
- Qualifications: 3+ years in CPU RTL design; strong skills in Verilog, System Verilog, or VHDL.
The predicted salary is between 60000 - 80000 £ per year.
Responsibilities
- Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
- Integrate new design content into SiFive's Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
- Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
- Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
- Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
- Microarchitecture development and specification.
- Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.
Requirements
- BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
- 3+ years of design experience.
- Academic or professional experience with CPU RTL design.
- Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
- Strong software engineering skills/background, including object-oriented, aspect-oriented, and particularly functional programming.
- Templated metaprogramming in any language.
- Compiler infrastructures, particularly for domain-specific languages.
- Data modelling, particularly intermediate representations for optimizing or transforming compiler passes.
- Test-driven development, particularly ability to write adaptive unit tests.
- Attention to detail and a focus on high-quality design.
- Ability to work well with others and share the belief that engineering is teamwork.
Nice-to-haves
- Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software.
- Knowledge of RISC-V architecture.
- Expertise in CPU processor designs in one or more of the following areas is a plus: instruction fetch, instruction decode, register renaming and instruction scheduling, vector units, load-store unit.
- Knowledge of verification principles, testbenches, UVM, and coverage.
- Experience with Git/Github, Jira, Confluence.
This position requires a successful background and reference checks and satisfactory proof of your right to work in the United Kingdom. Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer.
Senior RTL Design Engineer - CPU in Cambridge employer: SiFive UK Ltd.
SiFive is an exceptional employer for Senior RTL Design Engineers, offering a dynamic work environment that fosters innovation and collaboration in the heart of the UK tech scene. With a strong emphasis on employee growth, SiFive provides opportunities for professional development through hands-on experience with cutting-edge RISC-V CPU designs and a culture that values teamwork and knowledge sharing. Employees enjoy competitive benefits and the chance to contribute to groundbreaking technology while working alongside industry experts.
StudySmarter Expert Advice🤫
We think this is how you could land Senior RTL Design Engineer - CPU in Cambridge
✨Tip Number 1
Network like a pro! Reach out to folks in the industry, attend meetups, and connect with people on LinkedIn. You never know who might have the inside scoop on job openings or can refer you directly.
✨Tip Number 2
Show off your skills! Create a portfolio showcasing your projects, especially those related to CPU design or RTL. This gives potential employers a tangible look at what you can do and sets you apart from the crowd.
✨Tip Number 3
Prepare for interviews by brushing up on technical questions related to RISC-V architecture and hardware design. Practice explaining your past projects and how they relate to the role you're applying for—confidence is key!
✨Tip Number 4
Don’t forget to apply through our website! It’s the best way to ensure your application gets seen. Plus, we love seeing candidates who are proactive about their job search.
We think you need these skills to ace Senior RTL Design Engineer - CPU in Cambridge
Some tips for your application 🫡
Tailor Your CV:Make sure your CV is tailored to the Senior RTL Design Engineer role. Highlight your experience with CPU RTL design and any relevant projects you've worked on. We want to see how your skills align with our needs!
Showcase Your Skills:Don’t just list your skills; demonstrate them! Include specific examples of your work with Verilog, System Verilog, or VHDL. We love seeing how you’ve applied your knowledge in real-world scenarios.
Craft a Compelling Cover Letter:Your cover letter is your chance to shine! Use it to explain why you're passionate about CPU design and how you can contribute to our team. We appreciate a personal touch that shows us who you are.
Apply Through Our Website:We encourage you to apply through our website for a smoother process. It helps us keep track of your application and ensures you don’t miss out on any important updates from us!
How to prepare for a job interview at SiFive UK Ltd.
✨Know Your Stuff
Make sure you brush up on your knowledge of CPU RTL design, especially in Verilog, System Verilog, or VHDL. Be ready to discuss your past projects and how they relate to the responsibilities outlined in the job description.
✨Show Off Your Collaboration Skills
Since engineering is all about teamwork, be prepared to share examples of how you've worked with others in the past. Highlight any experiences where you contributed to collaborative design efforts or shared knowledge through documentation.
✨Prepare for Technical Questions
Expect some technical questions related to RISC-V architecture and performance optimisation. Brush up on your understanding of microarchitecture development and be ready to explain your thought process when tackling design challenges.
✨Demonstrate Your Problem-Solving Skills
Be ready to discuss how you approach verification test plans and sandbox verification. Share specific examples of how you've used test-driven development and adaptive unit tests to ensure high-quality design in your previous roles.
