Senior CPU RTL Engineer (RISC‑V, Chisel)
Senior CPU RTL Engineer (RISC‑V, Chisel)

Senior CPU RTL Engineer (RISC‑V, Chisel)

Full-Time 60000 - 80000 £ / year (est.) No home office possible
SiFive, Inc.

At a Glance

  • Tasks: Architect and implement features in RISC-V CPU core generators.
  • Company: Leading technology company specialising in CPU design.
  • Benefits: Competitive salary, flexible working hours, and opportunities for professional growth.
  • Why this job: Join a cutting-edge team and shape the future of CPU technology.
  • Qualifications: 3+ years of design experience and strong hardware design skills.
  • Other info: Collaborative environment with a focus on innovation and detail.

The predicted salary is between 60000 - 80000 £ per year.

A technology company specializing in CPU design is seeking a Senior RTL Design Engineer in Cambridge. You will be responsible for architecting and implementing features in RISC-V CPU core generators.

The ideal candidate has 3+ years of design experience and a strong background in hardware design with Verilog/System Verilog or VHDL. Excellent collaboration skills and attention to detail are essential, and experience with tools like Git, Jira, and Confluence is preferred.

Senior CPU RTL Engineer (RISC‑V, Chisel) employer: SiFive, Inc.

Join a leading technology company in Cambridge that fosters innovation and collaboration in CPU design. We offer a dynamic work culture that prioritises employee growth through continuous learning opportunities and mentorship, alongside competitive benefits that support work-life balance. As a Senior CPU RTL Engineer, you will be part of a forward-thinking team dedicated to pushing the boundaries of technology in a vibrant city known for its rich academic and tech community.
SiFive, Inc.

Contact Detail:

SiFive, Inc. Recruiting Team

StudySmarter Expert Advice 🤫

We think this is how you could land Senior CPU RTL Engineer (RISC‑V, Chisel)

Tip Number 1

Network like a pro! Reach out to your connections in the tech industry, especially those who work with RISC-V or CPU design. A friendly chat can lead to insider info about job openings that might not even be advertised yet.

Tip Number 2

Show off your skills! Prepare a portfolio showcasing your previous projects in hardware design, especially any work with Verilog/System Verilog or VHDL. This will give potential employers a clear view of what you can bring to the table.

Tip Number 3

Ace the interview! Brush up on your technical knowledge and be ready to discuss your experience with tools like Git, Jira, and Confluence. Don’t forget to highlight your collaboration skills – teamwork is key in this field!

Tip Number 4

Apply through our website! We make it super easy for you to submit your application directly. Plus, it shows us you're genuinely interested in joining our team. So, don’t hesitate – get your application in today!

We think you need these skills to ace Senior CPU RTL Engineer (RISC‑V, Chisel)

RISC-V
RTL Design
Verilog
System Verilog
VHDL
Collaboration Skills
Attention to Detail
Git
Jira
Confluence
Hardware Design
Architecting Features
Implementation Skills

Some tips for your application 🫡

Tailor Your CV: Make sure your CV highlights your experience with RISC-V and any relevant hardware design projects. We want to see how your skills align with the role, so don’t be shy about showcasing your expertise in Verilog/System Verilog or VHDL!

Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re passionate about CPU design and how your background makes you a perfect fit for our team. We love seeing enthusiasm and a personal touch!

Show Off Your Collaboration Skills: Since we value teamwork, make sure to mention any experiences where you’ve successfully collaborated with others. Whether it’s using tools like Git, Jira, or Confluence, let us know how you’ve worked effectively in a team setting.

Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it’s super easy – just follow the prompts!

How to prepare for a job interview at SiFive, Inc.

Know Your RISC-V Inside Out

Make sure you brush up on your knowledge of RISC-V architecture and its core features. Be prepared to discuss how you've implemented or worked with RISC-V in your previous roles, as this will show your expertise and passion for the technology.

Showcase Your Design Experience

Highlight your experience with Verilog/System Verilog or VHDL during the interview. Bring examples of past projects where you’ve successfully designed and implemented hardware solutions, and be ready to explain your design choices and the impact they had on the project.

Collaboration is Key

Since excellent collaboration skills are essential, think of examples where you’ve worked effectively in a team. Be ready to discuss how you’ve used tools like Git, Jira, and Confluence to enhance teamwork and project management in your previous roles.

Attention to Detail Matters

Prepare to demonstrate your attention to detail by discussing specific instances where your meticulousness made a difference in your work. Whether it was debugging a complex issue or ensuring compliance with design specifications, these examples will showcase your commitment to quality.

Senior CPU RTL Engineer (RISC‑V, Chisel)
SiFive, Inc.

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