SiFive Inc. is seeking an experienced engineer to architect and implement features and ISA extensions for RISC-V CPU core generators using Chisel.
You’ll integrate design content into the Chisel/FIRRTL framework, help automate documentation and tests, and collaborate across verification and physical design teams to optimize performance, area, and power. Strong RTL experience and ISA knowledge are essential.
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Senior RTL Design Engineer - RISC-V & Chisel Expert in Saffron Walden employer: SiFive, Inc.
SiFive is an exceptional employer, renowned for its commitment to innovation and collaboration in the tech industry. Located in Cambridge, England, employees benefit from a vibrant work culture that fosters creativity and teamwork, alongside opportunities for professional growth in cutting-edge semiconductor technology. With a focus on functional safety and a supportive environment, SiFive empowers its team members to make a meaningful impact on the future of computing.
