Senior RTL Design Engineer - CPU in London
Senior RTL Design Engineer - CPU

Senior RTL Design Engineer - CPU in London

London Full-Time 60000 - 80000 £ / year (est.) No home office possible
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SiFive, Inc.

At a Glance

  • Tasks: Design cutting-edge CPU cores using revolutionary RISC-V architecture.
  • Company: Join SiFive, a pioneer in RISC-V technology and innovation.
  • Benefits: Competitive salary, inclusive culture, and opportunities for professional growth.
  • Why this job: Be part of a team that transforms the future of computing.
  • Qualifications: 3+ years in CPU RTL design and strong software engineering skills.
  • Other info: Dynamic environment with a focus on collaboration and groundbreaking ideas.

The predicted salary is between 60000 - 80000 £ per year.

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive's unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are. Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

Job Description:

The Role

As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open-source RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Responsibilities

  • Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
  • Integrate new design content into SiFive's Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
  • Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
  • Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
  • Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
  • Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.

Requirements

  • BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
  • 3+ years of design experience.
  • Academic or professional experience with CPU RTL design.
  • Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
  • Strong software engineering skills/background, including:
  • Object-oriented, aspect-oriented, and particularly functional programming
  • Templated metaprogramming, in any language
  • Compiler infrastructures, particularly for domain-specific languages
  • Data modeling, particularly intermediate representations for optimizing or transforming compiler passes
  • Test-driven development, particularly ability to write adaptive unit tests
  • Attention to detail and a focus on high-quality design.
  • Ability to work well with others and share the belief that engineering is teamwork.
  • Nice-to-haves

    • Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software.
    • Knowledge of RISC-V architecture.
    • Expertise in CPU processor designs in one or more of the following areas is a plus: instruction fetch; instruction decode; register renaming and instruction scheduling; vector units; load-store unit.
    • Knowledge of verification principles, testbenches, UVM, and coverage.
    • Experience with Git/Github, Jira, Confluence.

    Additional Information:

    This position requires a successful background and reference checks and satisfactory proof of your right to work in the United Kingdom. Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

    SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

    Senior RTL Design Engineer - CPU in London employer: SiFive, Inc.

    SiFive is an exceptional employer located in Cambridge, England, offering a dynamic work environment where innovation thrives. Employees benefit from a collaborative culture that encourages teamwork and creativity, alongside opportunities for professional growth in cutting-edge CPU design using the revolutionary RISC-V architecture. With a commitment to diversity and inclusion, SiFive not only fosters a supportive atmosphere but also provides the chance to contribute to groundbreaking technology that impacts lives globally.
    SiFive, Inc.

    Contact Detail:

    SiFive, Inc. Recruiting Team

    StudySmarter Expert Advice 🤫

    We think this is how you could land Senior RTL Design Engineer - CPU in London

    ✨Tip Number 1

    Network like a pro! Reach out to current or former employees at SiFive on LinkedIn. A friendly chat can give you insider info and maybe even a referral, which can really boost your chances.

    ✨Tip Number 2

    Prepare for the interview by brushing up on your technical skills. Make sure you can talk confidently about CPU design and RISC-V architecture. We want to see your passion and expertise shine through!

    ✨Tip Number 3

    Showcase your projects! If you've worked on any relevant designs or have personal projects that highlight your skills in RTL design, bring them up during your interview. It’s a great way to demonstrate your hands-on experience.

    ✨Tip Number 4

    Don’t forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, it shows you’re genuinely interested in joining the SiFive team.

    We think you need these skills to ace Senior RTL Design Engineer - CPU in London

    CPU RTL Design
    Verilog
    System Verilog
    VHDL
    Chisel
    FIRRTL
    Microarchitecture Development
    Performance Optimization
    Test-Driven Development
    Collaboration
    RISC-V Architecture
    UVM
    Git/Github
    Jira
    Confluence

    Some tips for your application 🫡

    Tailor Your CV: Make sure your CV is tailored to the Senior RTL Design Engineer role. Highlight your experience with CPU RTL design and any relevant projects you've worked on. We want to see how your skills align with our needs!

    Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Share your passion for RISC-V architecture and why you’re excited about joining SiFive. Let us know how you can contribute to our innovative team.

    Showcase Your Technical Skills: Don’t forget to mention your proficiency in Verilog, System Verilog, or VHDL. If you have experience with Scala/Chisel, make it known! We love seeing candidates who are technically savvy and ready to dive into complex challenges.

    Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it shows you’re keen on joining our team!

    How to prepare for a job interview at SiFive, Inc.

    ✨Know Your RISC-V Inside Out

    Make sure you brush up on your knowledge of the RISC-V architecture. Understand its principles and how it differs from other architectures. Being able to discuss its advantages and potential applications will show your passion and expertise.

    ✨Showcase Your RTL Design Skills

    Prepare to discuss your experience with RTL design in Verilog, System Verilog, or VHDL. Bring examples of past projects where you implemented features or optimised designs. This will demonstrate your hands-on experience and problem-solving abilities.

    ✨Collaboration is Key

    SiFive values teamwork, so be ready to talk about how you've worked with others in previous roles. Share specific examples of how you contributed to a team project, especially in areas like verification or performance modelling.

    ✨Ask Insightful Questions

    Prepare thoughtful questions about SiFive's current projects or future directions in CPU design. This shows your genuine interest in the company and helps you gauge if it's the right fit for you. Plus, it opens up a dialogue that can make you more memorable.

    Senior RTL Design Engineer - CPU in London
    SiFive, Inc.
    Location: London
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