Senior CPU RTL Engineer (RISC‐V, Chisel) in London
Senior CPU RTL Engineer (RISC‐V, Chisel)

Senior CPU RTL Engineer (RISC‐V, Chisel) in London

London Full-Time 60000 - 80000 £ / year (est.) No home office possible
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SiFive, Inc.

At a Glance

  • Tasks: Architect and implement features in RISC-V CPU core generators.
  • Company: Leading tech company focused on innovative CPU design.
  • Benefits: Competitive salary, flexible working hours, and opportunities for professional growth.
  • Why this job: Join a cutting-edge team and shape the future of CPU technology.
  • Qualifications: 3+ years in hardware design with Verilog/System Verilog or VHDL.
  • Other info: Collaborative environment with a focus on innovation and detail.

The predicted salary is between 60000 - 80000 £ per year.

A technology company specializing in CPU design is seeking a Senior RTL Design Engineer in Cambridge. You will be responsible for architecting and implementing features in RISC-V CPU core generators.

The ideal candidate has 3+ years of design experience and a strong background in hardware design with Verilog/System Verilog or VHDL. Excellent collaboration skills and attention to detail are essential, and experience with tools like Git, Jira, and Confluence is preferred.

Senior CPU RTL Engineer (RISC‐V, Chisel) in London employer: SiFive, Inc.

Join a leading technology company in Cambridge that fosters innovation and collaboration in CPU design. With a strong emphasis on employee growth, we offer comprehensive training programmes and opportunities to work on cutting-edge projects in RISC-V architecture. Our inclusive work culture values creativity and teamwork, making it an ideal environment for talented engineers looking to make a meaningful impact.
SiFive, Inc.

Contact Detail:

SiFive, Inc. Recruiting Team

StudySmarter Expert Advice 🤫

We think this is how you could land Senior CPU RTL Engineer (RISC‐V, Chisel) in London

Tip Number 1

Network like a pro! Reach out to your connections in the tech industry, especially those who work with RISC-V or CPU design. A friendly chat can lead to insider info about job openings that might not even be advertised yet.

Tip Number 2

Show off your skills! If you’ve got a portfolio of projects or contributions to open-source hardware design, make sure to highlight them. This is your chance to demonstrate your expertise in Verilog/System Verilog or VHDL.

Tip Number 3

Prepare for the interview like it’s a big game! Research the company and its products, especially their RISC-V CPU core generators. Be ready to discuss how your experience aligns with their needs and how you can contribute to their team.

Tip Number 4

Don’t forget to apply through our website! We’re always on the lookout for talented individuals like you. It’s the best way to ensure your application gets the attention it deserves.

We think you need these skills to ace Senior CPU RTL Engineer (RISC‐V, Chisel) in London

RISC-V
RTL Design
Verilog
System Verilog
VHDL
Collaboration Skills
Attention to Detail
Git
Jira
Confluence
Hardware Design
Architecting Features
Implementation Skills

Some tips for your application 🫡

Tailor Your CV: Make sure your CV highlights your experience with RISC-V and RTL design. We want to see how your skills align with the role, so don’t be shy about showcasing your projects and achievements!

Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re passionate about CPU design and how your background in Verilog/System Verilog or VHDL makes you a perfect fit for us.

Show Off Your Collaboration Skills: Since we value teamwork, mention any experiences where you’ve successfully collaborated on projects. Highlighting your use of tools like Git, Jira, and Confluence can really set you apart!

Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you don’t miss out on any important updates from our team!

How to prepare for a job interview at SiFive, Inc.

Know Your RISC-V Inside Out

Make sure you brush up on your knowledge of RISC-V architecture and its core features. Be prepared to discuss how you've implemented RISC-V in past projects, as well as any challenges you've faced and how you overcame them.

Showcase Your RTL Design Skills

Be ready to dive deep into your experience with Verilog/System Verilog or VHDL. Prepare specific examples of your work, focusing on the design decisions you made and the impact they had on the project. This will demonstrate your expertise and problem-solving abilities.

Collaboration is Key

Since excellent collaboration skills are essential for this role, think of examples where you've successfully worked in a team. Highlight your experience with tools like Git, Jira, and Confluence, and be ready to discuss how these tools have facilitated your teamwork.

Attention to Detail Matters

Prepare to discuss how your attention to detail has contributed to the success of your projects. Bring up instances where your meticulousness helped catch potential issues early or improved the overall quality of your designs.

Senior CPU RTL Engineer (RISC‐V, Chisel) in London
SiFive, Inc.
Location: London
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