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- Tasks: Design and implement cutting-edge CPU cores using revolutionary RISC-V architecture.
- Company: Join SiFive, a pioneer in RISC-V technology, transforming the future of computing.
- Benefits: Competitive salary, inclusive culture, and opportunities for professional growth.
- Why this job: Be part of a dynamic team driving innovation in high-performance computing.
- Qualifications: 5+ years in CPU RTL design; strong skills in Verilog or System Verilog.
- Other info: Collaborative environment with a focus on groundbreaking ideas and solutions.
The predicted salary is between 70000 - 90000 £ per year.
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are. Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Job Description:
The Role: As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open-source RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.
Responsibilities
- Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
- Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
- Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
- Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
- Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
- Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.
Requirements
- BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
- 5+ years of design experience.
- Academic or professional experience with CPU RTL design.
- Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
- Strong software engineering skills/background, including:
- Object-oriented, aspect-oriented, and particularly functional programming
- Templated metaprogramming, in any language
- Compiler infrastructures, particularly for domain-specific languages
- Data modeling, particularly intermediate representations for optimizing or transforming compiler passes
- Test-driven development, particularly ability to write adaptive unit tests
Nice-to-haves
- Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software.
- Knowledge of RISC-V architecture.
- Expertise in CPU processor designs in one or more of the following areas is a plus: instruction decode; register renaming, reorder buffer, and instruction scheduling; vector units; load-store unit.
- Knowledge of verification principles, testbenches, UVM, and coverage.
- Experience with Git/Github, Jira, Confluence.
This position requires a successful background and reference checks and satisfactory proof of your right to work in the United Kingdom. Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Staff RTL Design Engineer - CPU Midcore in Cambridge employer: SiFive, Inc.
Contact Detail:
SiFive, Inc. Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Staff RTL Design Engineer - CPU Midcore in Cambridge
✨Tip Number 1
Network like a pro! Reach out to folks in the industry, attend meetups, and connect with current SiFive employees on LinkedIn. A personal connection can make all the difference when it comes to landing that interview.
✨Tip Number 2
Show off your skills! If you’ve got a portfolio of projects or contributions to open-source, make sure to highlight them. This is your chance to demonstrate your expertise in CPU RTL design and RISC-V architecture.
✨Tip Number 3
Prepare for technical interviews by brushing up on your knowledge of Verilog, System Verilog, and Chisel. Practice coding challenges and be ready to discuss your past projects in detail—this is where we can really shine!
✨Tip Number 4
Don’t forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, it shows you’re genuinely interested in joining the SiFive team.
We think you need these skills to ace Staff RTL Design Engineer - CPU Midcore in Cambridge
Some tips for your application 🫡
Tailor Your CV: Make sure your CV is tailored to the Staff RTL Design Engineer role. Highlight your experience with CPU RTL design and any relevant projects you've worked on. We want to see how your skills align with our needs!
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Share your passion for RISC-V architecture and why you’re excited about joining SiFive. Let us know how you can contribute to our innovative team.
Showcase Your Technical Skills: Don’t forget to mention your proficiency in Verilog, System Verilog, or VHDL. If you have experience with Scala/Chisel or any other relevant tools, make sure to include that too. We love seeing your technical prowess!
Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it’s super easy!
How to prepare for a job interview at SiFive, Inc.
✨Know Your RISC-V Inside Out
Make sure you brush up on your knowledge of the RISC-V architecture. Understand its principles and how it differs from other architectures. Be ready to discuss how you can contribute to SiFive's innovative projects using this technology.
✨Showcase Your RTL Design Skills
Prepare to talk about your experience with RTL design, particularly in Verilog or System Verilog. Have specific examples ready that demonstrate your ability to architect and implement features, as well as any challenges you've overcome in past projects.
✨Collaboration is Key
SiFive values teamwork, so be prepared to discuss how you've worked effectively in teams before. Share examples of how you’ve collaborated with verification teams or physical implementation teams to achieve project goals.
✨Ask Insightful Questions
Prepare thoughtful questions about SiFive’s projects, culture, and future directions. This shows your genuine interest in the role and helps you assess if the company is the right fit for you.