SiFive is seeking a hardware design engineer passionate about debug, trace and profiling IP to support the adoption of RISC-V for SOC designs. The engineer will lead enhancements and develop new capabilities, collaborating with customers, partners, tools vendors and the RISC‑V International Association.
The focus is on debug, trace and profiling hardware, with challenges spanning configurable RTL generators, Chisel/FIRRTL integration, and verification.
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Senior Debug, Trace & Profiling Hardware Architect in Cambridge employer: SiFive, Inc.
SiFive is an exceptional employer, renowned for its commitment to innovation and collaboration in the tech industry. Located in Cambridge, England, employees benefit from a vibrant work culture that fosters creativity and teamwork, alongside opportunities for professional growth in cutting-edge semiconductor technology. With a focus on functional safety and a supportive environment, SiFive empowers its team members to make a meaningful impact on the future of computing.
