Senior CPU RTL Engineer (RISC‑V, Chisel) in Cambridge
Senior CPU RTL Engineer (RISC‑V, Chisel)

Senior CPU RTL Engineer (RISC‑V, Chisel) in Cambridge

Cambridge Full-Time 60000 - 80000 £ / year (est.) No home office possible
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SiFive, Inc.

At a Glance

  • Tasks: Architect and implement features in RISC-V CPU core generators.
  • Company: Leading tech company in CPU design based in Cambridge.
  • Benefits: Competitive salary, flexible working hours, and opportunities for professional growth.
  • Why this job: Join a cutting-edge team and shape the future of CPU technology.
  • Qualifications: 3+ years in hardware design with Verilog/System Verilog or VHDL.
  • Other info: Collaborative environment with a focus on innovation and detail.

The predicted salary is between 60000 - 80000 £ per year.

A technology company specializing in CPU design is seeking a Senior RTL Design Engineer in Cambridge. You will be responsible for architecting and implementing features in RISC-V CPU core generators.

The ideal candidate has 3+ years of design experience and a strong background in hardware design with Verilog/System Verilog or VHDL. Excellent collaboration skills and attention to detail are essential, and experience with tools like Git, Jira, and Confluence is preferred.

Senior CPU RTL Engineer (RISC‑V, Chisel) in Cambridge employer: SiFive, Inc.

Join a leading technology company in Cambridge that fosters innovation and collaboration in CPU design. With a strong emphasis on employee growth, we offer comprehensive training programmes and opportunities to work on cutting-edge projects in RISC-V architecture. Our inclusive work culture values creativity and teamwork, making it an ideal environment for talented engineers looking to make a meaningful impact.
SiFive, Inc.

Contact Detail:

SiFive, Inc. Recruiting Team

StudySmarter Expert Advice 🤫

We think this is how you could land Senior CPU RTL Engineer (RISC‑V, Chisel) in Cambridge

Tip Number 1

Network like a pro! Reach out to your connections in the tech industry, especially those who work with RISC-V or CPU design. A friendly chat can lead to insider info about job openings that might not even be advertised yet.

Tip Number 2

Show off your skills! Prepare a portfolio showcasing your previous projects in hardware design, especially any work with Verilog/System Verilog or VHDL. This will give potential employers a clear view of what you can bring to the table.

Tip Number 3

Ace the interview! Brush up on your technical knowledge and be ready to discuss your experience with tools like Git, Jira, and Confluence. Don’t forget to highlight your collaboration skills – they’re just as important as your technical prowess!

Tip Number 4

Apply through our website! We make it super easy for you to submit your application directly. Plus, it shows us you're genuinely interested in joining our team. So, don’t hesitate – get your application in today!

We think you need these skills to ace Senior CPU RTL Engineer (RISC‑V, Chisel) in Cambridge

RISC-V
RTL Design
Verilog
System Verilog
VHDL
Collaboration Skills
Attention to Detail
Git
Jira
Confluence
Hardware Design
Architecting Features
Implementation Skills

Some tips for your application 🫡

Tailor Your CV: Make sure your CV highlights your experience with RISC-V and hardware design. We want to see how your skills align with the role, so don’t be shy about showcasing your 3+ years of relevant experience!

Show Off Your Collaboration Skills: Since we value teamwork, include examples of how you've worked effectively with others in past projects. Mention any tools like Git, Jira, or Confluence that you’ve used to enhance collaboration.

Attention to Detail is Key: In the world of CPU design, every detail matters! Make sure your application is free from typos and clearly structured. This shows us that you take pride in your work and understand the importance of precision.

Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it’s super easy!

How to prepare for a job interview at SiFive, Inc.

Know Your RISC-V Inside Out

Make sure you brush up on your knowledge of RISC-V architecture and its core features. Be prepared to discuss how you've implemented RISC-V in past projects, as well as any challenges you've faced and how you overcame them.

Showcase Your RTL Design Experience

Highlight your experience with Verilog/System Verilog or VHDL during the interview. Bring examples of your previous work, especially any complex designs you've worked on, and be ready to explain your design choices and the impact they had on the project.

Collaboration is Key

Since excellent collaboration skills are essential, think of examples where you've successfully worked in a team. Be ready to discuss how you’ve used tools like Git, Jira, and Confluence to enhance teamwork and project management.

Attention to Detail Matters

Prepare to demonstrate your attention to detail by discussing specific instances where this skill has made a difference in your work. Whether it’s catching bugs in your code or ensuring compliance with design specifications, having concrete examples will impress your interviewers.

Senior CPU RTL Engineer (RISC‑V, Chisel) in Cambridge
SiFive, Inc.
Location: Cambridge
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