SiFive is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to help design industry-leading CPU and interconnect IP for RISC-V based SOCs. You will work with architecture and design teams to implement core clocking, reset and power-management solutions and improve time-to-market.
The ideal candidate has 3+ years in CPU/SoC clocking and power-management, RTL design in Verilog/SystemVerilog or VHDL, and strong verification collaboration.
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Power & Clocking IP Design Engineer for RISC-V SoCs in Cambridge employer: SiFive, Inc.
SiFive is an exceptional employer, renowned for its commitment to innovation and collaboration in the tech industry. Located in Cambridge, England, employees benefit from a vibrant work culture that fosters creativity and teamwork, alongside opportunities for professional growth in cutting-edge semiconductor technology. With a focus on functional safety and a supportive environment, SiFive empowers its team members to make a meaningful impact on the future of computing.
