Senior ALU & Arithmetic HW Engineer (RISC-V) in Cambridge

Senior ALU & Arithmetic HW Engineer (RISC-V) in Cambridge

Cambridge Full-Time 54000 - 66000 Β£ / year (est.) Home office (partial)
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At a Glance

  • Tasks: Design and implement new arithmetic operators for RISC-V instructions.
  • Company: SiFive, Inc., a leader in innovative semiconductor solutions.
  • Benefits: Hybrid working model, competitive salary, and opportunities for professional growth.
  • Other info: Collaborative environment with a focus on optimisation and innovation.
  • Why this job: Join a cutting-edge team and shape the future of computing technology.
  • Qualifications: Master's degree in electronic engineering and experience in RTL design.

The predicted salary is between 54000 - 66000 Β£ per year.

Si Five, Inc. is seeking a Senior ALU Design Engineer based in Cambridge, England.

The successful candidate will specify, design and implement new arithmetic operators for RISC-V instructions.

With a focus on optimization, the role requires collaboration across various teams and a strong mathematical background.

This is a hybrid working position with a minimum of one office day per week.

Candidates should have a Master's degree in electronic engineering or a related field with extensive experience in RTL design and programming languages like Chisel or Verilog.

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Senior ALU & Arithmetic HW Engineer (RISC-V) in Cambridge employer: SiFive, Inc.

SiFive, Inc. is an exceptional employer that fosters a collaborative and innovative work culture in the heart of Cambridge, England. With a strong emphasis on employee growth, SiFive offers opportunities for professional development and the chance to work on cutting-edge technology in the RISC-V ecosystem. The hybrid working model ensures flexibility while maintaining a vibrant office environment, making it an ideal place for engineers looking to make a meaningful impact in their field.

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Contact Details:

SiFive, Inc. Recruitment Team

We think you need these skills to ace Senior ALU & Arithmetic HW Engineer (RISC-V) in Cambridge

ALU Design
RISC-V Architecture
RTL Design
Chisel
Verilog
Mathematical Background
Optimization Techniques