Senior Verification Engineer — Hybrid IP/SoC Testing
Senior Verification Engineer — Hybrid IP/SoC Testing

Senior Verification Engineer — Hybrid IP/SoC Testing

Full-Time 48000 - 72000 £ / year (est.) No home office possible
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At a Glance

  • Tasks: Develop verification strategies and create testbenches using SystemVerilog.
  • Company: Global technology leader in the UK with a focus on innovation.
  • Benefits: Flexible work environment, great rewards, and comprehensive benefits.
  • Why this job: Join a passionate team and contribute to groundbreaking technology projects.
  • Qualifications: Solid understanding of UVM and experience with EDA simulation tools.
  • Other info: Ideal for tech enthusiasts looking for a dynamic career.

The predicted salary is between 48000 - 72000 £ per year.

A global technology leader in the UK is seeking Digital Design or Verification Engineers to verify silicon IP. Responsibilities include developing verification strategies and creating testbenches using SystemVerilog. Candidates should have a solid understanding of UVM, as well as experience with EDA simulation tools. The role offers a flexible work environment with great benefits and rewards. This position is ideal for those passionate about technology and eager to contribute to groundbreaking projects.

Senior Verification Engineer — Hybrid IP/SoC Testing employer: Siemens AG

As a global technology leader based in the UK, we pride ourselves on fostering a dynamic and inclusive work culture that encourages innovation and collaboration. Our employees enjoy a flexible hybrid work environment, comprehensive benefits, and ample opportunities for professional growth, making it an ideal place for passionate individuals to thrive while contributing to cutting-edge projects in silicon IP verification.
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Contact Detail:

Siemens AG Recruiting Team

StudySmarter Expert Advice 🤫

We think this is how you could land Senior Verification Engineer — Hybrid IP/SoC Testing

Tip Number 1

Network like a pro! Reach out to current or former employees in the industry on LinkedIn. A friendly chat can give us insider info about the company culture and maybe even a referral!

Tip Number 2

Prepare for those technical interviews! Brush up on your SystemVerilog and UVM knowledge. We can even set up mock interviews with friends or colleagues to get comfortable with the questions you might face.

Tip Number 3

Showcase your passion for technology! During interviews, share personal projects or experiences that highlight your skills in verification and testing. It’s all about demonstrating how we can contribute to those groundbreaking projects.

Tip Number 4

Don’t forget to apply through our website! It’s the best way to ensure your application gets noticed. Plus, we often have exclusive opportunities listed there that you won’t find anywhere else.

We think you need these skills to ace Senior Verification Engineer — Hybrid IP/SoC Testing

Digital Design
Verification Engineering
Silicon IP Verification
Verification Strategies Development
Testbench Creation
SystemVerilog
UVM
EDA Simulation Tools
Problem-Solving Skills
Attention to Detail
Technical Aptitude
Communication Skills
Adaptability

Some tips for your application 🫡

Tailor Your CV: Make sure your CV highlights your experience with SystemVerilog and UVM. We want to see how your skills align with the role, so don’t be shy about showcasing relevant projects or achievements!

Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Tell us why you’re passionate about technology and how you can contribute to our groundbreaking projects. Keep it engaging and personal – we love to see your personality!

Showcase Your Technical Skills: In your application, mention any EDA simulation tools you’ve worked with. We’re looking for candidates who can hit the ground running, so let us know how your technical expertise can benefit our team.

Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for this exciting opportunity. Plus, it’s super easy!

How to prepare for a job interview at Siemens AG

Know Your Tech Inside Out

Make sure you brush up on your knowledge of SystemVerilog and UVM. Be ready to discuss how you've used these tools in past projects, as well as any challenges you've faced and how you overcame them.

Showcase Your Problem-Solving Skills

Prepare to talk about specific instances where you've developed verification strategies or created testbenches. Use the STAR method (Situation, Task, Action, Result) to structure your answers and highlight your contributions.

Familiarise Yourself with EDA Tools

Since experience with EDA simulation tools is crucial, make sure you can discuss the tools you've used and how they fit into your verification process. If possible, bring examples of how these tools have helped you achieve successful outcomes.

Emphasise Your Passion for Technology

This role is perfect for those who are passionate about technology. Be prepared to share what excites you about the field and how you stay updated with the latest trends and advancements in silicon IP verification.

Senior Verification Engineer — Hybrid IP/SoC Testing
Siemens AG
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  • Senior Verification Engineer — Hybrid IP/SoC Testing

    Full-Time
    48000 - 72000 £ / year (est.)
  • S

    Siemens AG

    250,000+
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