Own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems, including PCIe, CXL, and UALink, across multiple silicon products. Translate system and protocol requirements into implementation-ready microarchitecture specifications, interfaces, register definitions, and synthesizable RTL, ensuring detailed execution and delivery.
Drive the development process from concept through RTL creation, subsystem integration, verification support, synthesis preparation, and final delivery. Collaborate with architecture, verification, performance, firmware, physical design, and implementation teams to meet functionality, bandwidth, latency, power, area, and timing targets, encouraging a culture of inclusion and teamwork.
Analyze traffic patterns, workloads, queue depths, credits, outstanding transactions, and buffer requirements to guide implementation tradeoffs. Lead technical reviews, debug cross-functional issues, improve building methodologies, and mentor engineers, ensuring outstanding performance and reliability.
#J-18808-Ljbffr
PRINCIPAL DESIGN ENGINEER – HIGH-SPEED INTERCONNECT in Cambridge employer: Semiconductor Engineering
As a leading innovator in the semiconductor industry, our company offers an exceptional work environment for Senior/Staff Subsystem & SoC Design Engineers. Located in a vibrant tech hub, we foster a collaborative culture that encourages creativity and professional growth, providing ample opportunities for skill development and career advancement. With competitive benefits and a commitment to work-life balance, we ensure our employees thrive both personally and professionally while contributing to cutting-edge projects.
